US-12628448-B2 - Fast charge transfer floating diffusion region for a photodetector and methods of forming the same

US12628448B2US 12628448 B2US12628448 B2US 12628448B2US-12628448-B2

Abstract

A subpixel including at least one second-conductivity-type pinned photodiode layer that forms a p-n junction with a substrate semiconductor layer, at least one floating diffusion region, and at least one transfer gate stack structure. The at least one transfer gate stack structure may at least partially laterally surround the at least one second-conductivity-type pinned photodiode layer with a total azimuthal extension angle in a range from 240 degrees to 360 degrees around a geometrical center of the second-conductivity-type pinned photodiode layer. The at least one transfer gate stack structure may include multiple edges that overlie different segments of a periphery of the at least one second-conductivity-type pinned photodiode layer, and the floating diffusion region includes a portion located between the first edge and the second edge. In addition, multiple transfer gate stack structures and multiple floating diffusion regions may be present in the subpixel.

Inventors

Feng-Chien Hsieh
Yun-Wei Cheng
Wei-Li Hu
Kuo-Cheng Lee
Hsin-Chi Chen

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Dates

Publication Date: 20260512
Application Date: 20230725

Claims (20)

1 . A semiconductor structure comprising at least one instance of a subpixel located on a semiconductor substrate including a substrate semiconductor layer having a doping of a first-conductivity-type, wherein each instance of the subpixel comprises: at least one second-conductivity-type pinned photodiode layer that forms at least one p-n junction with the substrate semiconductor layer; a floating diffusion region that is laterally spaced from the at least one second-conductivity-type pinned photodiode layer; and a transfer gate stack structure including a transfer gate dielectric and a transfer gate electrode and located between the floating diffusion region and each of the at least one second-conductivity-type pinned photodiode layer, and having a first edge that overlies a first segment of at least one periphery of the at least one second-conductivity-type pinned photodiode layer and a second edge that overlies a second segment of the at least one periphery of the at least one second-conductivity-type pinned photodiode layer, wherein the floating diffusion region comprises a portion located between the first edge and the second edge.
2 . The semiconductor structure of claim 1 , wherein the first edge of the transfer gate stack structure and the second edge of the transfer gate stack structure are parallel to each other.
3 . The semiconductor structure of claim 1 , wherein: the transfer gate stack structure comprises a third edge that is adjoined to the first edge and comprises a fourth edge that is adjoined to the second edge; an angle between the third edge and the first edge is in a range from 45 degrees to 135 degrees; and an angle between the fourth edge and the second edge is in a range from 45 degrees to 135 degrees.
4 . The semiconductor structure of claim 1 , wherein a geometrical center of the at least one second-conductivity-type pinned photodiode layer is located outside the at least one second-conductivity-type pinned photodiode layer, and is located within, or underlies, the transfer gate stack structure or the floating diffusion region.
5 . The semiconductor structure of claim 1 , wherein the at least one second-conductivity-type pinned photodiode layer comprises a single continuous second-conductivity-type pinned photodiode layer including each portion of the at least one second-conductivity-type pinned photodiode layer.
6 . The semiconductor structure of claim 1 , wherein at least one second-conductivity-type pinned photodiode layer comprises a plurality of second-conductivity-type pinned photodiode layers that do not directly contact each other or one another, and are laterally spaced apart by a semiconductor material portion that underlies the transfer gate stack structure and having a doping of the first-conductivity-type.
7 . The semiconductor structure of claim 1 , wherein: the semiconductor structure comprises an image sensor comprising an array of pixels located on the semiconductor substrate; the at least one instance of the subpixel comprises a plurality of subpixels located within a respective pixel in the array of pixels; and each pixel within the array of pixels comprises a respective instance of the subpixel.
8 . A semiconductor structure comprising at least one instance of a subpixel located on a semiconductor substrate including a substrate semiconductor layer having a doping of a first-conductivity-type, wherein each instance of the subpixel comprises: at least one second-conductivity-type pinned photodiode layer that forms at least one p-n junction with the substrate semiconductor layer; a floating diffusion region that is laterally spaced from the at least one second-conductivity-type pinned photodiode layer and comprising a first portion in contact with a metal via structure and a second portion that laterally protrudes outward from the first portion and having a uniform width between a pair of lengthwise sidewalls; and a transfer gate stack structure including a transfer gate dielectric and a transfer gate electrode and located between the floating diffusion region and each of the at least one second-conductivity-type pinned photodiode layer, wherein the transfer gate structure comprises a pair of laterally-extending segments that overlie a respective one of the pair of lengthwise sidewalls of the second portion of the floating diffusion region.
9 . The semiconductor structure of claim 8 , wherein a geometrical center of the at least one second-conductivity-type pinned photodiode layer is located outside a volume of the at least one second-conductivity-type pinned photodiode layer and within an area of the second portion of the floating diffusion region in a plan view.
10 . The semiconductor structure of claim 8 , wherein: the pair of laterally-extending segments comprises a first straight edge that overlies a first region of the at least one second-conductivity-type pinned photodiode layer and a second straight edge that overlies a second region of the at least one second-conductivity-type pinned photodiode layer; and the first edge and the second edge of the transfer gate stack structure are parallel to each other.
11 . The semiconductor structure of claim 10 , wherein: the first portion of the transfer gate stack structure comprises a third straight edge that is adjoined to the first straight edge and further comprises a fourth straight edge that is adjoined to the second straight edge; an angle between the third straight edge and the first straight edge is in a range from 45 degrees to 135 degrees; and an angle between the fourth straight edge and the second straight edge is in a range from 45 degrees to 135 degrees.
12 . The semiconductor structure of claim 11 , wherein the first portion of the transfer gate stack structure comprises: a first additional straight edge that is adjoined to the third straight edge; a second additional straight edge that is adjoined to the fourth straight edge; and a connecting edge that connects the first straight edge and the second straight edge and comprising a non-planar vertical surface.
13 . The semiconductor structure of claim 8 , wherein the at least one second-conductivity-type pinned photodiode layer comprises a single continuous second-conductivity-type pinned photodiode layer that contacts each lengthwise sidewall within the pair of lengthwise sidewalls of the second portion of the floating diffusion region.
14 . The semiconductor structure of claim 8 , wherein at least one second-conductivity-type pinned photodiode layer comprises a plurality of second-conductivity-type pinned photodiode layers that do not directly contact each other or one another, and are laterally spaced apart by a portion of the substrate semiconductor layer that underlies the transfer gate stack structure and having a doping of the first-conductivity-type.
15 . A semiconductor structure comprising at least one instance of a subpixel located on a semiconductor substrate including a substrate semiconductor layer having a doping of a first-conductivity-type, wherein each instance of the subpixel comprises: a second-conductivity-type pinned photodiode layer that forms a p-n junction with the substrate semiconductor layer; floating diffusion regions that are laterally spaced from the second-conductivity-type pinned photodiode layer; and at least one transfer gate stack structure including a respective transfer gate dielectric and a respective transfer gate electrode and located between the second-conductivity-type pinned photodiode layer and a respective one of the floating diffusion regions.
16 . The semiconductor structure of claim 15 , wherein the floating diffusion regions do not contact each other or one another, and are electrically connected to each other or one another by a set of metal interconnect structures.
17 . The semiconductor structure of claim 15 , further comprising a shallow trench isolation structure that laterally surrounds, and contacts each of, the second-conductivity-type pinned photodiode layer and the floating diffusion regions.
18 . The semiconductor structure of claim 15 , wherein the at least one transfer gate stack structure comprises a plurality of transfer gate stack structures, and the transfer gate electrodes of the plurality of transfer gate stack structures are electrically connected to each other by a set of metal interconnect structures.
19 . The semiconductor structure of claim 15 , wherein the floating diffusion regions comprise three or more discrete floating diffusion regions that do not contact one another.
20 . The semiconductor structure of claim 15 , wherein: the semiconductor structure comprises an image sensor comprising an array of pixels located on the semiconductor substrate; the at least one instance of the subpixel comprises a plurality of subpixels located within a respective pixel in the array of pixels; and each pixel within the array of pixels comprises a respective instance of the subpixel.

Description

RELATED APPLICATIONS This application is a divisional application of U.S. application Ser. No. 17/182,300 entitled “Fast Charge Transfer Floating Diffusion Region for a Photodetector and Methods of Forming the Same,” filed on Feb. 23, 2021, the entire contents of which are incorporated herein by reference. BACKGROUND Semiconductor image sensors are used to sense electromagnetic radiation such as visible range light, infrared radiation, and/or ultraviolet light. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors are used in various applications. For example, such image sensors may be used in digital cameras or embedded cameras in mobile devices. These devices utilize an array of pixels (which may include photodiodes and transistors) to detect radiation using photogeneration of electron-hole pairs. A large p-n junction area may increase the photosensitivity in a photodetector. However, for such large p-n junction areas in a photodetector, the charge transfer speed to a floating diffusion region may be slow. Fast charge transfer to the floating diffusion region may increase the operational speed of a photodetector in CMOS image sensors. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A is a plan view of a first configuration for an array of pixels of an image sensor according to an embodiment of the present disclosure. FIG. 1B is a plan view of a second configuration for an array of pixels of an image sensor according to another embodiment of the present disclosure. FIG. 2A is a plan view of front side sensor components within the area of a subpixel in a first configuration of a first exemplary structure according to an embodiment of the present disclosure. FIG. 2B is a vertical cross-sectional view of the first exemplary structure along a hinged vertical plane B-B′-B″ that passes through the vertical axes B, B′, and B″ of FIG. 2A. FIG. 2C is a zoom-out plan view of the front side sensor components within a pixel in the first configuration of the first exemplary structure of FIGS. 2A and 2B. FIG. 2D is a plan view of front side sensor components within the area of a subpixel in a second configuration of the first exemplary structure according to an embodiment of the present disclosure. FIG. 2E is a plan view of front side sensor components within the area of a subpixel in a third configuration of the first exemplary structure according to an embodiment of the present disclosure. FIG. 2F is a plan view of front side sensor components within the area of a subpixel in a fourth configuration of the first exemplary structure according to an embodiment of the present disclosure. FIG. 3A is a plan view of front side sensor components within the area of a subpixel in a first configuration of a second exemplary structure according to an embodiment of the present disclosure. FIG. 3B is a plan view of front side sensor components within the area of a subpixel in a second configuration of the second exemplary structure according to an embodiment of the present disclosure. FIG. 3C is a plan view of front side sensor components within the area of a subpixel in a third configuration of the second exemplary structure according to an embodiment of the present disclosure. FIG. 3D is a plan view of front side sensor components within the area of a subpixel in a fourth configuration of the second exemplary structure according to an embodiment of the present disclosure. FIG. 3E is a plan view of front side sensor components within the area of a subpixel in a fifth configuration of the second exemplary structure according to an embodiment of the present disclosure. FIG. 3F is a plan view of front side sensor components within the area of a subpixel in a sixth configuration of the second exemplary structure according to an embodiment of the present disclosure. FIG. 4A is a plan view of front side sensor components within the area of a subpixel in a first configuration of a third exemplary structure according to an embodiment of the present disclosure. FIG. 4B is a plan view of front side sensor components within the area of a subpixel in a second configuration of the third exemplary structure according to an embodiment of the present disclosure. FIG. 4C is a plan view of front side sensor components within the area of a subpixel in a third configuration of the third exemplary structure according to an embodiment of the present disclosure. FIG. 4D is a plan view of front side sensor components within the area of a subpixel in a fourth configuration of the third exemplary structure according to an embodiment of the present disc