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US-12628456-B2 - Integration of a detection circuit based on optical resonators interconnected on a readout circuit of an imager

US12628456B2US 12628456 B2US12628456 B2US 12628456B2US-12628456-B2

Abstract

An optoelectronic device includes at least one pixel comprising: a plurality of optical resonators, each optical resonator comprising a photodetecting structure confined between a first reflective metal layer and a second metal layer; and a connection microstructure that is arranged on a support made of dielectric material and is configured to electrically interconnect the second metal layers of the optical resonators belonging to the same pixel; and a readout integrated circuit arranged on a substrate and assembled with the pixel; the readout circuit comprising a buried readout electrode associated with the pixel and a metal or dielectric outer layer. The assembly comprising at least the first metal layer and the outer layer of the readout integrated circuit is called a planar assembly structure. The second metal layers of the resonators of a pixel are connected to the associated readout electrode by way of a metal via connected to the connection microstructure and passing through the support.

Inventors

  • ALEXANDRE DELGA
  • Roch ESPIAU DE LAMAESTRE

Assignees

  • THALES
  • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Dates

Publication Date
20260512
Application Date
20211221
Priority Date
20201223

Claims (19)

  1. 1 . An optoelectronic device (OPT) comprising: at least one pixel (Pxl), a pixel comprising: a plurality of optical resonators (RO 1 , RO 2 ), each optical resonator comprising a photodetecting structure (SPD) confined between a first, reflective, metal layer (M 1 ) and a second metal layer (M 2 ); and a connection microstructure (MC) that is arranged on a support made of dielectric material and is configured to electrically interconnect the second metal layers (M 2 ) of the optical resonators (RO 1 , RO 2 ) belonging to the same pixel (Pxl); a readout integrated circuit (ROIC) arranged on a substrate (Sub 2 ) and assembled with said pixel; the readout integrated circuit comprising a buried readout electrode (EL) associated with said pixel (Pxl) and a metal or dielectric outer layer (M 3 , D 2 ); the assembly comprising at least the first metal layer (M 1 ) and the outer layer (M 3 ) of the readout integrated circuit being referred to as planar assembly structure (SPA); the second metal layers (M 2 ) of the resonators (RO 1 , RO 2 ) of a pixel (Pxl) being connected to the associated readout electrode (EL) by way of a metal via (V 1 ) connected to the connection microstructure (MC) and passing through the support.
  2. 2 . The optoelectronic device (OPT) as claimed in claim 1 , wherein at least one dimension of a resonator (RO i ), chosen from among width and length, is within the interval [λ/2n−50%; λ/2n+50%], where: λ is an incident wavelength; n is an effective refractive index of the photodetecting structure (SPD).
  3. 3 . The optoelectronic device (OPT) as claimed in claim 1 , wherein the height of the photodetecting structure (SPD) is within the interval [λ/4n−50%; λ/2n+50%], where: λ is an incident wavelength; n is an effective refractive index of the photodetecting structure (SPD).
  4. 4 . The optoelectronic device (OPT) as claimed in claim 1 , wherein the distance between two adjacent pixels (Pxl) is greater than or equal to the wavelength absorbed by an optical resonator (RO 1 , RO 2 ) divided by twice the effective refractive index of the photodetecting structure (SPD).
  5. 5 . The optoelectronic device (OPT) as claimed in claim 1 , wherein the metal via (V 1 ) is electrically isolated from the reflective metal layers (M 1 ) of the resonators (RO 1 , RO 2 ) of said pixel (Pxl).
  6. 6 . The optoelectronic device (OPT) as claimed in claim 1 , wherein the second metal layer (M 2 ) covers the entire surface ( 20 A) of the photodetecting structure (SPD).
  7. 7 . The optoelectronic device (OPT) as claimed in claim 1 , wherein the second metal layer (M 2 ) covers part of the surface ( 20 A) of the photodetecting structure (SPD); the second metal layer (M 2 ) being fully covered by an encapsulating layer made of dielectric material (ENC).
  8. 8 . The optoelectronic device (OPT) as claimed in claim 7 , furthermore comprising an etch stop ring (AG) made of a dielectric material arranged on the surface ( 20 A) of the photodetecting structure (SPD).
  9. 9 . The optoelectronic device (OPT) as claimed in claim 1 , wherein: the outer layer of the readout integrated circuit (ROIC) is a metal layer (M 3 ) common to all of the resonators (RO 1 , RO 2 ) of said at least one pixel (Pxl), and to all of the pixels (Pxl) where applicable, said metal outer layer (M 3 ) being connected to electrical ground; the reflective metal layer (M 1 ) is common to all of the resonators (RO 1 , RO 2 ) of said at least one pixel (Pxl), and to all of the pixels (Pxl) where applicable; and the metal via (V 1 ) passes through said assembly structure (SPA) and part of the readout integrated circuit (ROIC) to the readout electrode (EL).
  10. 10 . The optoelectronic device (OPT) as claimed in claim 1 , wherein the planar assembly structure (SPA) is structured so as to form individualized elementary assembly structures (SPAI) for each electrode (EL); said elementary assembly structures (SPAI) being electrically isolated from one another; an elementary assembly structure (SPAI) associated with an electrode (EL) of a pixel (Pxl) being electrically connected to said electrode (EL) and to the metal via (V 1 ) of said pixel (Pxl).
  11. 11 . A matrix image sensor comprising an optoelectronic device (OPT) as claimed in claim 1 .
  12. 12 . A process for manufacturing an optoelectronic device (OPT), the process comprising the steps of: assembling a first planar structure (S 1 ) comprising a first substrate (Sub 1 ), an assembly of at least one photodetecting layer (CPD) and a first reflective metal layer (M 1 ), on the one hand; and a readout integrated circuit (ROIC) deposited on a second substrate (Sub 2 ) and comprising at least one buried readout electrode (EL) and a metal or dielectric outer layer (M 3 ), on the other hand; the assembly comprising at least the first metal layer (M 1 ) and the outer layer (M 3 , D 2 ) of the readout integrated circuit (ROIC) forming a planar assembly structure (SPA), the planar assembly structure (SPA) being either continuous (SPAC) or structured (SPAS) and comprising individualized elementary assembly structures (SPAI) that are electrically isolated from one another; when the planar assembly structure (SPAC) is continuous, the buried readout electrode (EL) is electrically isolated from the continuous planar assembly structure (SPAC); when the planar assembly structure (SPAS) is structured, the buried readout electrode (EL) is electrically connected to an elementary assembly structure: detaching the first substrate (Sub 1 ); producing at least one pixel (Pxl) associated with a buried electrode (EL), comprising the sub-steps of: producing a plurality of optical resonators (RO i ) by: selectively etching each of the layers of said assembly of at least one photodetecting layer (CPD) to produce a plurality of photodetecting structures (SPD); depositing a second metal layer (M 2 ) on each photodetecting structure (SPD); when the planar assembly structure (SPAS) is structured, the photodetecting structure (SPD) is located facing an individualized elementary assembly structure (SPAI); producing a support made of dielectric material between the resonators and connecting said optical resonators (RO i ) to one another by way of a connection microstructure (MC) arranged on said support; producing a metal via (V 1 ) passing through the support so as to connect the second metal layers (M 2 ) of the resonators to the associated buried electrode (EL) via the connection microstructure (MC).
  13. 13 . The process for manufacturing an optoelectronic device (OPT) as claimed in claim 12 , wherein, when the planar assembly structure (SPAC) is continuous, the step of producing the metal via (V 1 ) comprises the sub-steps of: etching a via hole (IH) passing through the assembly structure (SPAC) to the buried electrode (EL); filling the via hole (IH) with a conductive material in order to electrically connect the second metal layers (M 2 ) to the buried electrode (EL); the step of producing the support being such that said support does not cover the via hole (IH).
  14. 14 . The process for manufacturing an optoelectronic device (OPT) as claimed in claim 12 , wherein, when the planar assembly structure (SPAS) is structured, the step of producing the metal via (V 1 ) comprises the sub-steps of: etching a via hole (IH) passing through the support to the elementary assembly structure (SPAI) connected to the buried electrode (EL); filling the via hole (IH) with a conductive material in order to electrically connect the second metal layers (M 2 ) to the elementary assembly structure (SPAI) connected to the buried electrode (EL).
  15. 15 . The process for manufacturing an optoelectronic device (OPT) as claimed in claim 12 , furthermore comprising a step of encapsulating the pixel (Pxl), comprising the following sub-steps: depositing an encapsulating layer made of dielectric material (ENC) covering the second metal layers (M 2 ) and the connection microstructure (MC); selectively etching the encapsulating layer (ENC) so as to retain at least the parts covering the first metal layer (M 1 ) and the connection microstructure (MC).
  16. 16 . The process for manufacturing an optoelectronic device (OPT) as claimed in claim 15 , comprising: a step of depositing an etch stop layer (CAG) on an outer layer of said assembly of at least one photodetecting layer (CPD) prior to the step of producing at least one pixel (Pxl) associated with a buried electrode (EL); and wherein the step of producing at least one pixel (Pxl) furthermore comprises the following sub-steps: selectively etching the etch stop layer (CAG) so as to produce, for each resonator, an etch stop ring (AG) arranged on part of the surface of the photodetecting structure (SPD) serving to contain the first metal layer (M 1 ).
  17. 17 . The process for manufacturing an optoelectronic device (OPT) as claimed in claim 15 , wherein the conductive material deposited to produce the second metal layer (M 2 ) and the metal via (V 1 ) is copper or aluminum or tungsten.
  18. 18 . The process for manufacturing an optoelectronic device (OPT) as claimed in claim 12 , wherein the conductive material deposited to produce the second metal layer (M 2 ) and the metal via (V 1 ) is gold or titanium or platinum.
  19. 19 . The process as claimed in claim 12 , wherein the step of producing a plurality of optical resonators (RO i ) and the step of producing the metal via (V 1 ) are carried out by lithography then etching, the lithography technology being chosen from among: electron beam; nanoprinting; optical lithography, and the etching technology being chosen from among ion etching, chemical etching or plasma.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a National Stage of International patent application PCT/EP2021/087001, filed on Dec. 21, 2021, which claims priority to foreign French patent application No. FR 2014012, filed on Dec. 23, 2020, the disclosures of which are incorporated by reference in their entireties. FIELD OF THE INVENTION The invention relates to hybrid systems, that is to say systems formed of two separate parts that are assembled by an assembly layer, each part being made of a different material. These systems may be optical, electronic or optoelectronic depending on the features of the assembled parts. The invention relates in particular to the integration of a plurality of metal-insulator-metal optical resonators on a readout integrated circuit for a matrix image sensor in the infrared region. The matrix imager is formed of a plurality of pixels, and each pixel comprises a plurality of interconnected optical resonators. BACKGROUND Hybrid systems make it possible to combine two functionalities implemented in different materials. These are for example: a detector, in which the sensitive part is associated with a readout circuit that makes it possible to collect and process the signal to be detected,a display, for example a light-emitting display, in which the emitting part is associated with a circuit for generating electrical signals suitable for emission,a photonic circuit, with laser emitters associated with layers for processing the emitted beams (guidance, multiplexing/demultiplexing, amplification, etc.), the one or more processing layers being deposited on a silicon substrate (“Photonic on Silicon”),an electronic circuit with fast transistors or power transistors associated with a control system. The first two hybrid systems may be described as optoelectronic, the third may be purely optical or optoelectronic, while the fourth is purely electronic. More specifically, the technical field in question is that of the production of hybrid optoelectronic systems, comprising: an optical part based on at least one photosensitive element for generating electric charge carriers from incident photons (for example a matrix of bolometers, photodiodes or photoconductors);and an electronic part consisting of a readout integrated circuit on a semiconductor substrate for individually reading the signal from each pixel of the optical part. A pixel belonging to the optoelectronic system may contain a single photosensitive element or a plurality of interconnected photosensitive elements. There are some imager technologies in which the photosensitive layer consists of a first family of semiconductor materials and the readout integrated circuit is formed in a substrate of a second family of semiconductor materials different from the first. The photodetectors are produced using III-V semiconductor materials such as gallium arsenide, indium arsenide, gallium nitride, gallium antimonide and boron phosphide. The photodetectors may also be produced using II-VI semiconductor materials. To build a hybrid system, it is necessary to assemble the photodetectors and to interconnect them with the readout integrated circuit on a silicon substrate. FIG. 1 illustrates a partial sectional view of a hybrid optoelectronic system according to the prior art, having an optical part comprising a metal diffraction grating behind each pixel. The optoelectronic device Dis1 illustrated in FIG. 1 is a vertical-transport infrared imager. It consists of an optical part OPT_D1 comprising at least one pixel Pxl_D1 and of an electronic part consisting of a readout integrated circuit ROIC_D1 comprising at least one buried electrode EL_D1. The readout integrated circuit ROIC_D1 is formed by a plurality of transistors and thin layers of conductive, semiconductor or dielectric CMOS-technology (Complementary Metal-Oxide-Semiconductor) material on a silicon substrate. A buried electrode EL_D1 is associated with each pixel Pxl_D1 in order to read the signals generated by the photo charge carriers generated by the photodetecting structure of a pixel Pxl_D1. With regard to the optical part of the device, this comprises a plurality of layers C1, C2, C3, with C1 and C3 being two conductive layers obtained by N+-doping a III-V (or II-VI) semiconductor material, and C2 being a semiconductor layer (C2 possibly being a stack of layers of III-V (or II-VI) semiconductor materials that is confined between the layers C1 and C3). The layer C2 acts as the photodetecting structure of the pixel Pxl_D1. A metal layer CM is deposited on the conductive layer C3 so as to form an upper metal contact that is associated exclusively with each pixel. The structuring of the interface C3/CM defines a diffraction grating. Each pixel of the optical part OPT_D1 is separated from an adjacent pixel of the matrix detector by way of a barrier made of dielectric material BMD. The lower layer C1 is common to a plurality of pixels and is connected to the electrical