US-12628457-B2 - Image sensors and methods of manufacturing the same

Abstract

An image sensor includes a chip structure including first and second regions. The chip structure further includes a substrate having a first surface, a second surface, and a recess portion, a plurality of photoelectric conversion devices included in the substrate, at least one conductive layer on a sidewall and a bottom surface of the recess portion and on the horizontal insulating layer in the second region, a first passivation layer on a side surface of the conductive layer in the recess portion and the conductive layer on the horizontal insulating layer, and a second passivation layer on side surface of the first passivation layer in the recess portion.

Inventors

• Hoemin JEONG
• Seungjoo NAH
• Heegeun JEONG
• Soongeul CHOI
• Dongmin Han

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20230627

Priority Date

20220628

Claims (20)

1. 1 . An image sensor comprising: a chip structure including a first region and a second region, the chip structure further comprising, a substrate having a first surface, a second surface, and a recess portion, the second surface opposite the first surface, and the recess portion recessed from the second surface in the second region; a plurality of photoelectric conversion devices included in the substrate in the first region; at least one horizontal insulating layer on the second surface of the substrate; a plurality of color filters on the at least one horizontal insulating layer in the first region; a grid pattern between the plurality of color filters on the at least one horizontal insulating layer; a plurality of microlenses on the plurality of color filters; at least one conductive layer on a sidewall and a bottom surface of the recess portion and on the at least one horizontal insulating layer in the second region; at least one conductive pad in contact with the at least one conductive layer in the recess portion; a first passivation layer on a side surface of the at least one conductive layer in the recess portion and the at least one conductive layer on the at least one horizontal insulating layer; and a second passivation layer on side surface of the first passivation layer in the recess portion.
2. 2 . The image sensor of claim 1 , wherein the second passivation layer has at least one protrusion extended toward the first passivation layer from the side surface of the first passivation layer in the recess portion.
3. 3 . The image sensor of claim 2 , wherein the at least one protrusion has a convex shape and faces toward the side surface of the first passivation layer.
4. 4 . The image sensor of claim 2 , wherein the at least one protrusion is in contact with the at least one conductive layer.
5. 5 . The image sensor of claim 1 , wherein the first passivation layer includes: a first portion on a side surface of the at least one conductive layer, a second portion extended from the first portion to be on a bottom surface of the at least one conductive layer, and a third portion extended from the second portion to be on a side surface of the at least one conductive pad.
6. 6 . The image sensor of claim 5 , wherein the second passivation layer is on the first to third portions, and the second passivation layer is separated from the at least one conductive layer in the recess portion by the first passivation layer.
7. 7 . The image sensor of claim 5 , wherein an upper end of the third portion is on a level higher than a level of an upper surface of the at least one conductive pad.
8. 8 . The image sensor of claim 5 , wherein the first passivation layer further includes a fourth portion extended from the third portion and is on at least a portion of an upper surface of the at least one conductive pad, and the second passivation layer is on an upper surface of the fourth portion.
9. 9 . The image sensor of claim 1 , wherein the first passivation layer includes a same material as the grid pattern.
10. 10 . The image sensor of claim 1 , wherein the chip structure further comprises: a first chip structure; and a second chip structure on the first chip structure, wherein the first chip structure comprises: a first substrate; and a first interconnection structure on the first substrate, wherein the second chip structure comprises the substrate, the plurality of photoelectric conversion devices, the at least one horizontal insulating layer, the plurality of color filters, the grid pattern, the at least one conductive layer, the at least one conductive pad, the first passivation layer, and the second passivation layer, wherein the second chip structure further comprises a second interconnection structure between the first chip structure and the substrate, wherein the chip structure further comprises a via hole penetrating through the substrate and exposing a pad of the first interconnection structure, and wherein the at least one conductive layer further comprises a portion on a side surface and a bottom surface of the via hole and contacting the pad of the first interconnection structure.
11. 11 . The image sensor of claim 1 , wherein the second passivation layer includes a same material as the plurality of microlenses.
12. 12 . The image sensor of claim 1 , wherein a thickness of the second passivation layer is higher than a thickness of the first passivation layer.
13. 13 . The image sensor of claim 1 , wherein the chip structure further includes a third region between the first region and the second region, the chip structure further includes a light blocking pattern, the light blocking pattern on the at least one horizontal insulating layer in the third region, and an upper capping layer on the light blocking pattern, and an upper surface of the second passivation layer is on a same level as an upper surface of the upper capping layer.
14. 14 . The image sensor of claim 1 , wherein the chip structure further includes a third region between the first region and the second region, the chip structure further includes a light blocking pattern, the light blocking pattern on the at least one horizontal insulating layer in the third region, and an upper capping layer on the light blocking pattern, and an upper surface of the second passivation layer is on a same level as an upper surface of the light blocking pattern.
15. 15 . An image sensor comprising: a semiconductor substrate having a first surface, a second surface, and a recess portion, the second surface opposite the first surface, and the recess portion extending inward towards the semiconductor substrate from the second surface; a plurality of photoelectric conversion devices included in the semiconductor substrate; a conductive layer on the second surface of the semiconductor substrate; a conductive pad in contact with the conductive layer in the recess portion; a first passivation layer on a portion of the second surface of the semiconductor substrate, a side surface of the recess portion, a portion of a bottom surface of the recess portion, and a side surface of the conductive pad; and a second passivation layer on an upper surface of the first passivation layer and at least a portion of the first passivation layer in the recess portion, wherein the conductive layer extends between the first passivation layer and the second surface of the semiconductor substrate, between the first passivation layer and a side surface of the recess portion, between the first passivation layer and a portion of the bottom surface of the recess portion, and between a lower surface of the conductive pad and a portion of the bottom surface of the recess portion.
16. 16 . The image sensor of claim 15 , wherein the second passivation layer is separated from the conductive layer in the recess portion by the first passivation layer.
17. 17 . The image sensor of claim 15 , wherein the second passivation layer includes a protrusion directed toward the first passivation layer, and the protrusion is on a level lower than a level of an uppermost portion of the first passivation layer.
18. 18 . An image sensor comprising: a chip structure, the chip structure including a first region and a second region, wherein the chip structure further comprises, an upper substrate having a first surface, a second surface, and a recess portion, the second surface opposite the first surface, and the recess portion recessed from the second surface in the second region; a plurality of photoelectric conversion devices included in the upper substrate in the first region; a horizontal insulating layer on the second surface of the upper substrate; a conductive layer on a side surface and a bottom surface of the recess portion and at least a portion of the horizontal insulating layer in the second region; at least one conductive pad in contact with the conductive layer in the recess portion; a first passivation layer on a side surface of the conductive layer in the recess portion and the conductive layer on the horizontal insulating layer; and a second passivation layer on a side surface of the first passivation layer in the recess portion, and the second passivation layer includes a first protrusion extended toward the first passivation layer from the side surface of the first passivation layer, the second passivation layer including a material having a step coverage higher than a step coverage of a material of the first passivation layer.
19. 19 . The image sensor of claim 18 , wherein the conductive layer has an end portion which is configured to expose a portion of the horizontal insulating layer in the second region, and the first passivation layer is on the end portion and the exposed portion of the horizontal insulating layer.
20. 20 . The image sensor of claim 19 , wherein the second passivation layer includes a second protrusion extended toward the first passivation layer toward the end portion.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This U.S. non-provisional application claims the benefit of priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0078721 filed on Jun. 28, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND Various example embodiments of the inventive concepts relate to image sensors, systems including the image sensors, and/or methods of manufacturing the image sensors. An image sensor is a semiconductor-based sensor receiving light to generate an electrical signal and may include a pixel array having a plurality of pixels, logic circuits for driving the pixel array and generating an image, and the like. Each of the plurality of pixels may include a photodiode, a pixel circuit converting a charge generated by the photodiode into an electrical signal, and the like. SUMMARY Various example embodiments provide an image sensor having improved productivity and/or reliability, a system including the image sensor, and/or methods of manufacturing the image sensor. According to at least one example embodiment, an image sensor includes a chip structure including a first region and a second region, the chip structure further comprising, a substrate having a first surface, a second surface, and a recess portion, the second surface opposite the first surface, and the recess portion recessed from the second surface in the second region, a plurality of photoelectric conversion devices included in the substrate in the first region, at least one horizontal insulating layer on the second surface of the substrate, a plurality of color filters on the horizontal insulating layer in the first region, a grid pattern between the plurality of color filters on the horizontal insulating layer, a plurality of microlenses on the plurality of color filters, at least one conductive layer on a sidewall and a bottom surface of the recess portion and on the horizontal insulating layer in the second region, at least one conductive pad in contact with the conductive layer in the recess portion, a first passivation layer on a side surface of the conductive layer in the recess portion and the conductive layer on the horizontal insulating layer, and a second passivation layer on side surface of the first passivation layer in the recess portion. According to at least one example embodiment, an image sensor includes a semiconductor substrate having a first surface, a second surface, and a recess portion, the second surface opposite the first surface, and the recess portion extending inward towards the semiconductor substrate from the second surface, a plurality of photoelectric conversion devices included in the semiconductor substrate, a conductive layer on a second surface of the semiconductor substrate, a conductive pad in contact with the conductive layer in the recess portion, a first passivation layer on a portion of the second surface of the semiconductor substrate, a side surface of the recess portion, a portion of a bottom surface of the recess portion, and a side surface of the conductive pad, and a second passivation layer on an upper surface of the first passivation layer and at least a portion of the first passivation layer in the recess portion, wherein the conductive layer extends between the first passivation layer and the second surface of the semiconductor substrate, between the first passivation layer and a side surface of the recess portion, between the first passivation and a portion of the bottom surface of the recess portion, and between a lower surface of the conductive pad and a portion of the bottom surface of the recess portion. According to at least one example embodiment, an image sensor includes a chip structure, the chip structure including a first region and a second region, wherein the chip structure further comprises, an upper substrate having a first surface, a second surface, and a recess portion, the second surface opposite the first surface, and the recess portion recessed from the second surface in the second region, a plurality of photoelectric conversion devices included in the upper substrate in the first region, a horizontal insulating layer on the second surface of the upper substrate, a conductive layer on a side surface and a bottom surface of the recess portion and at least a portion of the horizontal insulating layer in the second region, at least one conductive pad in contact with the conductive layer in the recess portion, a first passivation layer on a side surface of the conductive layer in the recess portion and the conductive layer on the horizontal insulating layer, and a second passivation layer on a side surface of the first passivation layer in the recess portion, and the second passivation layer includes a first protrusion extended toward the first passivation layer from the side surface of the first passivation layer, the second passivation layer including a m