US-12628467-B2 - Heterogeneous chip integration of III-nitride-based materials for optoelectronic device arrays in the visible and ultraviolet

Abstract

Aspects of the subject disclosure may include, for example, bonding III-Nitride epitaxial layer(s) to a carrier wafer, wherein the III-Nitride epitaxial layer(s) are grown on a non-native substrate, after the bonding, removing at least a portion of the non-native substrate from the III-Nitride epitaxial layer(s), processing the III-Nitride epitaxial layer(s) to derive an array of III-Nitride islands, establishing a metal layer over the array of III-Nitride islands, resulting in an array of metal-coated III-Nitride islands, arranging the carrier wafer relative to a host wafer to position the array of metal-coated III-Nitride islands on a surface of the host wafer, causing the array of metal-coated III-Nitride islands and the surface of the host wafer to eutectically bond, and removing the carrier wafer to yield an integrated arrangement of III-Nitride islands on the host wafer. Additional embodiments are disclosed.

Inventors

• John Michael Dallesasse
• John A. Carlson

Assignees

• THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS

Dates

Publication Date

20260512

Application Date

20220225

Claims (20)

1. 1 . A method comprising: bonding one or more III-Nitride epitaxial layers to a carrier wafer, wherein the one or more III-Nitride epitaxial layers are grown on a non-native substrate; after the bonding, removing at least a portion of the non-native substrate from the one or more III-Nitride epitaxial layers; processing the one or more III-Nitride epitaxial layers to derive an array of III-Nitride islands; establishing a metal layer over the array of III-Nitride islands, resulting in an array of metal-coated III-Nitride islands; arranging the carrier wafer relative to a host wafer to position the array of metal-coated III-Nitride islands on a surface of the host wafer; causing the array of metal-coated III-Nitride islands and the surface of the host wafer to eutectically bond; removing the carrier wafer to yield an integrated arrangement of III-Nitride islands on the host wafer; obtaining a second device that includes a second carrier wafer having a second array of metal-coated III-Nitride islands, wherein the second device is derived according to one or more steps that correspond to one or more of the bonding, the removing of the at least a portion of the non-native substrate, the processing, and the establishing; using an optical alignment tool to align the second carrier wafer relative to the host wafer to position the second array of metal-coated III-Nitride islands on the surface of the host wafer relative to the integrated arrangement of III-Nitride islands; causing the second array of metal-coated III-Nitride islands and the surface of the host wafer to eutectically bond; and removing the second carrier wafer, thereby resulting in a further integrated arrangement of III-Nitride islands on the host wafer in which the second array of metal-coated III-Nitride islands is interleaved with the integrated arrangement of III-Nitride islands.
2. 2 . The method of claim 1 , wherein the arranging the carrier wafer relative to the host wafer comprises epitaxial transferring the array of metal-coated III-Nitride islands, in unison, onto the surface of the host wafer.
3. 3 . The method of claim 1 , wherein the processing the one or more III-Nitride epitaxial layers comprises performing photolithographic defining and etching to derive the array of III-Nitride islands.
4. 4 . The method of claim 1 , further comprising planarizing and patterning the integrated arrangement of III-Nitride islands to fabricate photonic pixels.
5. 5 . The method of claim 4 , wherein the photonic pixels are fabricated to provide functions relating to one or more of white light emission, ultraviolet (UV) light emission, chip-to-chip communications, visible light communications (VLC), and quantum information processing.
6. 6 . The method of claim 1 , wherein the bonding the one or more III-Nitride epitaxial layers to the carrier wafer is performed via a bonding polymer.
7. 7 . The method of claim 6 , further comprising, after the bonding the one or more III-Nitride epitaxial layers to the carrier wafer, removing excess portions of the bonding polymer.
8. 8 . The method of claim 7 , further comprising, after the processing the one or more III-Nitride epitaxial layers to derive the array of III-Nitride islands, removing additional portions of the bonding polymer based on locations of the III-Nitride islands.
9. 9 . The method of claim 8 , further comprising removing remaining portions of the bonding polymer to enable removal of the carrier wafer.
10. 10 . The method of claim 1 , wherein the one or more steps comprise: bonding additional III-Nitride epitaxial layers to the second carrier wafer, wherein the additional III-Nitride epitaxial layers are grown on a second non-native substrate; after the bonding the additional III-Nitride epitaxial layers to the second carrier wafer, removing at least a portion of the second non-native substrate from the additional III-Nitride epitaxial layers; processing the additional III-Nitride epitaxial layers to derive a second array of III-Nitride islands; and establishing a second metal layer over the second array of III-Nitride islands, resulting in the second array of metal-coated III-Nitride islands.
11. 11 . A heterogenous integration process, comprising: epitaxially bonding wide band gap semiconductor materials with a silicon carrier wafer, wherein the wide band gap semiconductor materials are grown on a non-native substrate; removing the non-native substrate from the wide band gap semiconductor materials; defining and deriving an array of wide band gap semiconductor islands; establishing a metal layer over the array of wide band gap semiconductor islands, resulting in an array of metal-coated wide band gap semiconductor islands; epitaxially transferring the array of metal-coated wide band gap semiconductor islands to a surface of a host wafer; forming a eutectic bond between the array of metal-coated wide band gap semiconductor islands and the surface of the host wafer, wherein one or more metal layer portions of the eutectic bond function as a mirror that provides reflectivity spanning a visible spectrum and an ultraviolet (UV) spectrum; removing the silicon carrier wafer; obtaining a second device that includes a second silicon carrier wafer having a second array of metal-coated wide band gap semiconductor islands, wherein the second device is derived according to one or more steps that correspond to one or more of the bonding, the removing of the non-native substrate, the defining and deriving, and the establishing; using an optical alignment tool to align the second silicon carrier wafer relative to the host wafer to position the second array of metal-coated wide band gap semiconductor islands on the surface of the host wafer relative to the array of metal-coated wide band gap semiconductor islands; causing the second array of metal-coated wide band gap semiconductor islands and the surface of the host wafer to eutectically bond; and removing the second silicon carrier wafer, thereby resulting in an integrated arrangement of wide band gap semiconductor islands on the host wafer in which the second array of metal-coated wide band gap semiconductor islands is interleaved with the array of metal-coated wide band gap semiconductor islands.
12. 12 . The heterogenous integration process of claim 11 , wherein the wide band gap semiconductor materials comprise III-Nitride epitaxial materials.
13. 13 . The heterogenous integration process of claim 11 , wherein the metal layer is composed of aluminum.
14. 14 . The heterogenous integration process of claim 13 , wherein the eutectic bond comprises an aluminum-silicon eutectic bond.
15. 15 . The heterogenous integration process of claim 11 , wherein eutectic bonding between the array of wide band gap semiconductor islands and the surface of the host wafer mechanically secures the array of wide band gap semiconductor islands to the host wafer, and forms one or more electrical interconnects for complementary metal-oxide-semiconductor (CMOS) and optoelectronic planes.
16. 16 . An integration method, comprising: epitaxially bonding III-Nitride materials with a silicon carrier wafer, wherein the III-Nitride materials are grown on a non-native substrate; removing the non-native substrate from the III-Nitride materials; defining and deriving an array of III-Nitride islands; establishing a metal layer over the array of III-Nitride islands, resulting in an array of metal-coated III-Nitride islands; epitaxially transferring the array of metal-coated III-Nitride islands to a surface of a host wafer; forming a eutectic bond between the array of metal-coated III-Nitride islands and the surface of the host wafer, thereby mechanically securing the array of metal-coated III-Nitride islands to the host wafer; removing the silicon carrier wafer to yield an integrated arrangement of III-Nitride islands on the host wafer; obtaining a second device that includes a second silicon carrier wafer having a second array of metal-coated III-Nitride islands, wherein the second device is derived according to one or more steps that correspond to one or more of the bonding, the removing, the defining and deriving, and the establishing; using an alignment tool to align the second silicon carrier wafer relative to the host wafer to position the second array of metal-coated III-Nitride islands on the surface of the host wafer relative to the integrated arrangement of III-Nitride islands; causing the second array of metal-coated III-Nitride islands and the surface of the host wafer to eutectically bond; and removing the second silicon carrier wafer, thereby resulting in a further integrated arrangement of III-Nitride islands on the host wafer in which the second array of metal-coated III-Nitride islands is interleaved with the integrated arrangement of III-Nitride islands.
17. 17 . The integration method of claim 16 , wherein the epitaxially transferring involves epitaxially transferring the array of metal-coated III-Nitride islands, in unison, onto the surface of the host wafer.
18. 18 . The integration method of claim 16 , wherein the metal layer is composed of aluminum.
19. 19 . The integration method of claim 18 , wherein the eutectic bond comprises an aluminum-silicon eutectic bond.
20. 20 . The integration method of claim 16 , wherein eutectic bonding between the array of metal-coated III-Nitride islands and the surface of the host wafer forms one or more electrical interconnects for complementary metal-oxide-semiconductor (CMOS) and optoelectronic planes, and functions as a mirror that provides reflectivity spanning a visible spectrum and an ultraviolet (UV) spectrum.

Description

CROSS REFERENCE TO RELATED APPLICATIONS The present application claims the benefit of priority to U.S. Provisional Application No. 63/185,800 filed on May 7, 2021 and U.S. Provisional Application No. 63/154,399 filed on Feb. 26, 2021. All sections of the aforementioned applications are incorporated herein by reference in their entirety. FIELD OF THE DISCLOSURE The subject disclosure generally relates to heterogeneous chip integration of III-Nitride-based materials for optoelectronic device arrays in the visible and/or ultraviolet (UV) spectrums. BACKGROUND Wide band gap semiconductors such as III-Nitride materials—e.g., aluminum nitride (AlN), indium nitride (InN), or gallium nitride (GaN)—are well-suited for modern electronic and optoelectronic applications. In fact, it is expected that III-Nitride-based light emitting diodes (LEDs) will replace traditional light bulbs and revolutionize lighting. Silicon (Si) is a preferred semiconductor material for heterogeneous integration because it is easily processed, it is readily available at reasonable cost and high quality, and complex, very large-scale integration (VLSI) electronic circuits are also readily available. However, it has been relatively difficult to integrate III-Nitride-based materials with electronic devices fabricated on silicon. Most active photonic devices require a single crystal material, which is difficult to grow on silicon due to the large lattice mismatch between the silicon and the semiconductor with the proper band gaps. BRIEF DESCRIPTION OF THE DRAWINGS Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein: FIGS. 1A-1H and 1J are diagrams illustrating, among other things, an example process flow of epitaxial bonding and epitaxial transfer for an individual arrangement of III-Nitride islands/pixels in accordance with various aspects described herein; FIG. 2A is an image of an example assembly of large-area bulk III-Nitride chiplets on a silicon carrier wafer in accordance with various aspects described herein; FIG. 2B is a cross-sectional diagram of example III-Nitride materials before and after substrate removal in accordance with various aspects described herein; FIG. 3 is a scanning electron micrograph of a result of an example epitaxial bonding process in accordance with various aspects described herein; FIG. 4 is a scanning electron micrograph of a result of an example epitaxial bonding and transfer process involving GaN high-electron-mobility transistor (HEMT) epitaxial structures in accordance with various aspects described herein; FIGS. 5A-5D are diagrams illustrating, among other things, an example process flow of heterogeneous island/pixel alignment in accordance with various aspects described herein; FIGS. 6A and 6B are diagrams illustrating, among other things, cross-sectional views of example III-Nitride optoelectronics embedded in/on a complementary metal-oxide-semiconductor (CMOS) platform for full electronic controls on a silicon substrate in accordance with various aspects described herein; FIG. 7 shows diagrams illustrating, among other things, partial cross-sectional views of example integrated metal-eutectic bond interface(s) serving as a high-reflectance mirror for broad spectrum in accordance with various aspects described herein; FIG. 8 is a graphical representation illustrating photoluminescence of example III-Nitride layers after full silicon substrate removal in accordance with various aspects described herein; FIG. 9 is a scanning electron micrograph of example epitaxially-transferred III-Nitride islands using an Al—Si eutectic in accordance with various aspects described herein; and FIG. 10 depicts an example, non-limiting method in accordance with various aspects described herein. DETAILED DESCRIPTION The subject disclosure describes, among other things, illustrative embodiments for heterogeneously integrating III-Nitride (or other wide band gap or group III-V) materials with a non-native substrate/wafer, such as that composed of silicon. Exemplary embodiments provide for large-scale integration of such materials onto a CMOS electronics platform in a scalable and integrative manner. In various embodiments, heterogenous integration may be realized by employing a sequence of techniques that includes epitaxial bonding and epitaxial transfer of one or more III-Nitride epitaxial materials. The III-Nitride epitaxial material(s) may be grown on any suitable substrate, such as a non-native substrate composed of silicon (e.g., silicon <100>, silicon <111>, or the like), silicon carbide, sapphire, diamond, bulk GaN, or the like. In a case where III-Nitride epitaxial layers are composed of GaN, indium gallium nitride (InGaN), indium aluminum nitride (InAlN), indium gallium aluminum nitride (InGaAlN), and/or AlN, for instance, a substrate composed of silicon, silicon carbide, sapphire, or diamond may be non-native to these III-Nitride epitaxial materials. In a cas