US-12628489-B2 - Transistor device

US12628489B2US 12628489 B2US12628489 B2US 12628489B2US-12628489-B2

Abstract

In an embodiment, a transistor device includes: a support layer having a first major surface and a second major surface opposing the first major surface; a source contact arranged on the first major surface of the support layer; a drain contact arranged on the second major surface of the support layer; and a gate electrode arranged in a first trench formed in the first major surface of the support layer. The first trench has a base and a side wall extending from the base to the first major surface. The drain contact is arranged under the base of the first trench. A region with gate-controlled conductivity is formed between the source contact and the drain contact. The region with gate-controlled conductivity is formed in an organic semiconductor layer.

Inventors

Michael Hutzler

Assignees

INFINEON TECHNOLOGIES AUSTRIA AG

Dates

Publication Date: 20260512
Application Date: 20231016
Priority Date: 20221103

Claims (16)

1 . A transistor device, comprising: a support layer having a first major surface and a second major surface opposing the first major surface; a source contact arranged on the first major surface of the support layer; a drain contact arranged on the second major surface of the support layer; a gate electrode arranged in a first trench formed in the first major surface of the support layer, the first trench having a base and a side wall extending from the base to the first major surface, wherein the drain contact is arranged under the base of the first trench; and a region with gate-controlled conductivity formed between the source contact and the drain contact, wherein the region with gate-controlled conductivity is formed in an organic semiconductor layer.
2 . The transistor device of claim 1 , wherein the support layer is formed of a dielectric material and the organic semiconductor layer is arranged on the base and sidewall of the first trench, wherein a gate dielectric layer is arranged on the organic semiconductor layer on the base and the side wall of the first trench and electrically insulates the gate electrode arranged in the first trench from the organic semiconductor layer.
3 . The transistor device of claim 2 , wherein the source contact is located adjacent the side wall of the first trench, the organic semiconductor layer further extends over a part of the source contact, and the gate dielectric layer extends over the organic semiconductor layer that is arranged on the source contact.
4 . The transistor device of claim 3 , further comprising: a source layer arranged on the source contact and between the source contact and the organic semiconductor layer that is arranged on the source contact; and a drain layer arranged on the drain contact.
5 . The transistor device of claim 1 , wherein the support layer is formed of an organic semiconductor and a gate dielectric layer is arranged on the base and side walls of the trench and electrically insulates the gate electrode from the support layer.
6 . The transistor device of claim 5 , wherein the source contact is located adjacent the side wall of the first trench and the gate dielectric layer further extends over a part of the source contact.
7 . The transistor device of claim 6 , further comprising a source layer arranged on the source contact between the source contact and the gate dielectric layer that is arranged on the source contact.
8 . The transistor device of claim 5 , wherein the support layer has an upper sublayer and a lower sublayer and the upper sublayer and the lower sublayer have different doping concentrations or the support layer comprises a vertical doping gradient.
9 . The transistor device of claim 5 , further comprising a field plate arranged in the first trench under the gate, the field plate being electrically insulated from the support layer by a field insulator.
10 . The transistor device of claim 9 , wherein the field plate is electrically insulated from the gate electrode by an intermediate insulating layer arranged in the first trench or the field plate is integral with the gate electrode.
11 . The transistor device of claim 5 , further comprising a second trench positioned laterally adjacent the first trench and that extends into the first major surface of the support layer and has a base and a side wall that extends from the base to the first major surface, wherein a field plate is arranged in the second trench and is electrically insulated from the support layer by a field insulator that lines the base and side walls of the second trench.
12 . The transistor device of claim 1 , wherein the first trench is elongate or columnar.
13 . The transistor device of claim 1 , further comprising a gate metal layer arranged on the gate electrode in the first trench, wherein the gate metal layer and the source contact each have an elongate strip-like structure and extend substantially parallel to one another on the first major surface of the support substrate.
14 . The transistor device of claim 13 , wherein the first trench is columnar and the gate metal layer extends over the first trench and electrically connects the first trench to another columnar trench.
15 . A method for fabricating a transistor device, the method comprising: forming a drain contact on a drain layer; forming an organic semiconductor layer on the drain contact; forming a source contact on the organic semiconductor layer; forming a source layer on the source contact; forming a first trench that extends through the source layer, the source contact and into the organic semiconductor layer, the first trench having a base and a side wall; forming a gate dielectric layer on the base and the side wall of the first trench; and forming a gate electrode on the gate dielectric layer in the first trench.
16 . A method for fabricating a transistor device, the method comprising: forming a drain contact on a drain layer; forming a dielectric layer on the drain contact; forming a source contact on the dielectric layer; forming a source layer on the source contact; forming a first trench that extends through the source layer, the source contact and into the dielectric layer, the first trench having a base and a side wall; forming an organic semiconductor layer on the base and the side wall of the first trench; forming a gate dielectric layer on the organic semiconductor layer; and forming a gate electrode on the gate dielectric layer in the first trench.

Description

BACKGROUND Transistors used in power electronic applications may be fabricated with silicon (Si) semiconductor materials. Common transistor devices for power applications include Si Power MOSFETs such as Si CoolMOS® and Si Insulated Gate Bipolar Transistors (IGBTs). Transistor devices may also be formed using other semiconductor materials including organic semiconductors. US 2006/0223218 A1 discloses a lateral field effect transistor with an organic semiconductor, in particular a device comprising a plurality of field effect transistors with an interconnect structure. The transistor is provided in a top-gate structure and the organic semiconductor layer and the dielectric layer are structured and patterned together. The semiconductor layer and the dielectric layer may be removed from areas not associated with field effect transistors or with crossing conductors of first and second conductor layers. The organic semiconductor material may be formed of pentacene, for example. Organic transistor devices may be used in displays, for example. It is desirable to provide organic transistor devices which are suitable for a use in a wider range of applications. SUMMARY In an exemplary embodiment, a transistor device comprises a support layer having a first major surface and a second major surface opposing the first major surface, a source contact arranged on the first major surface of the support layer, a drain contact arranged on the second major surface of the support layer and a gate electrode. The gate electrode is arranged in a first trench formed in the first major surface of the support layer, the first trench having a base and a side wall extending from the base to the first major surface. The drain contact is arranged under the base of the first trench. The transistor device further comprises a region with gate-controlled conductivity formed between the source contact and the drain contact. The region with gate-controlled conductivity is formed in an organic semiconductor layer. The transistor device can be considered to have a trench-based transistor structure and also a vertical trench-based transistor structure since the source and drain contacts are arranged on opposing major surfaces of the support layer. The organic semiconductor layer comprises the region with gate-controlled conductivity that provides the channel of the transistor. The organic semiconductor layer, in which the region with gate-controlled conductivity Is formed, may extend at least in part substantially perpendicularly between the first and second major surface of the support layer and between the source and drain contacts. A vertical organic semiconductor-based power FET is provided. The transistor device may comprise a plurality of transistor unit cells that are electrically connected in parallel such that high current levels can be switched. Each transistor unit cell comprises a source contact, a drain contact and a gate electrode arranged in a first trench. A single drain contact that is common to these transistor unit cells may be provided on the second major surface. A single source contact that is common to these transistor cells may be provided on the first major surface or one source contact for each transistor unit cell or one source contact for two adjoining transistor unit cells may be provided on the first major surface. In arrangements including two or more source contacts, these may be electrically connected together by a source bus that is arranged on the first major surface. The first trench comprises a side wall that extends from the base to the first major surface of the support layer. The base of the trench may be rounded or substantially planar and have an area that is substantially the same as the area of the opening of the trench at the first major surface, for example the difference between the area of the base and the area of the opening may be within ±10%. The sidewall may extend substantially perpendicularly to the first major surface. The drain contact is arranged under the base of the first trench and may extend under the entire width of the first trench. The drain contact may extend over the entire second major surface of the support layer. The organic semiconductor layer may comprise a conjugated polymer or small-molecule organic semiconductor. In some embodiments, the organic semiconductor comprises pentacene, poly (3-hexylthiophene) (P3HT), poly (3-alkylthiophene) (P3AT), poly (3-octylthiophene) (P3OT) or Poly-vinylephenyle (PVP). The organic semiconductor layer may have a first conductivity type, for example p-type. In some embodiments, the support layer is formed of a dielectric material and the organic semiconductor layer is arranged on the base and sidewall of the first trench. The dielectric material may be Poly-methyl-methacrylate (PMMA) or poly-ethylene-terephthalate (PET) or PVC (Poly Vinyl Chloride), for example. The organic semiconductor layer may have the form of a lining that lines the firs