US-12628507-B2 - Display substrate with bottom gate electrodes arranged in same layer, preparation method thereof, and display apparatus

Abstract

The present disclosure provides a display substrate, a preparation method thereof, and a display apparatus. The display substrate includes a base substrate and a drive structure layer disposed on the base substrate, wherein the drive structure layer includes a first transistor and a second transistor arranged side by side, the first transistor includes a low temperature poly silicon transistor, and the second transistor includes an oxide transistor; the first transistor includes a first bottom gate electrode simultaneously served as a shielding layer, the second transistor includes a second bottom gate electrode simultaneously served as a shielding layer, and the first bottom gate electrode and the second bottom gate electrode are arranged in a same layer.

Inventors

• Peng Huang
• Tao Gao
• Bingqiang GUI
• Ke Yang

Assignees

• CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
• BOE TECHNOLOGY GROUP CO., LTD.

Dates

Publication Date

20260512

Application Date

20210623

Claims (16)

1. 1 . A display substrate, comprising a base substrate and a drive structure layer disposed on the base substrate, wherein the drive structure layer comprises a first transistor and a second transistor arranged side by side, the first transistor comprises a low temperature poly silicon transistor, and the second transistor comprises an oxide transistor; the first transistor comprises a first bottom gate electrode simultaneously served as a shielding layer, the second transistor comprises a second bottom gate electrode simultaneously served as a shielding layer, and the first bottom gate electrode and the second bottom gate electrode are arranged in a same layer; wherein the drive structure layer comprises a first conductive layer disposed on the base substrate, an active structure layer disposed on a side of the first conductive layer away from the base substrate, and a source drain structure layer disposed on a side of the active structure layer away from the base substrate; the first conductive layer comprises the first bottom gate electrode and the second bottom gate electrode arranged in the same layer, the first bottom gate electrode and the second bottom gate electrode are formed simultaneously through a same patterning process; the active structure layer comprises a first active layer of the first transistor and a second active layer of the second transistor; wherein the source drain structure layer comprises: a fourth insulation layer disposed on a side of the active structure layer away from the base substrate, a source drain metal layer disposed on the fourth insulation layer; the source drain metal layer comprises a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, and a first connection electrode; the first source electrode and the first drain electrode are connected with the first active layer of the first transistor through a first via, the second source electrode and the second drain electrode are connected with the second active layer of the second transistor through a second via, and the first connection electrode is connected with the first bottom gate electrode of the first transistor through a third via; when the first via, the second via, and the third via are formed, the fourth insulation layer, a third insulation layer, and a second insulation layer in the first via are etched away to expose surfaces of a source region and a drain region on both sides of the first active layer, and the first via is a low temperature poly silicon CNT-L via; the fourth insulation layer and the third insulation layer in the second via are etched away to expose surfaces of a source region and a drain region on both sides of the second active layer, and the second via is an oxide CNT-O via; the fourth insulation layer, the third insulation layer, the second insulation layer, and a first insulation layer in the third via are etched away to expose a surface of the first bottom gate electrode; and the first via, the second via, and the third via are formed simultaneously through a same patterning process.
2. 2 . The display substrate according to claim 1 , wherein the active structure layer comprises: the first insulation layer covering the first conductive layer, the first active layer of the first transistor disposed on a side of the first insulation layer away from the base substrate, the second insulation layer covering the first active layer, a first top gate electrode of the first transistor disposed on a side of the second insulation layer away from the base substrate, the second active layer of the second transistor disposed on a side of the second insulation layer away from the base substrate, the third insulation layer covering the first gate top electrode and the second active layer, and a second top gate electrode of the second transistor disposed on a side of the third insulation layer away from the base substrate.
3. 3 . The display substrate according to claim 1 , wherein the active structure layer comprises: the first insulation layer covering the first conductive layer, the first active layer of the first transistor disposed on a side of the first insulation layer away from the base substrate, the second insulation layer covering the first active layer, the second active layer of the second transistor disposed on a side of the second insulation layer away from the base substrate, the third insulation layer covering the second active layer, and a first top gate electrode of the first transistor and a second top gate electrode of the second transistor disposed on a side of the third insulation layer away from the base substrate; the first top gate electrode and the second top gate electrode are arranged in a same layer.
4. 4 . The display substrate according to claim 1 , wherein a depth of the first via is 5000 Å to 9000 Å, and a depth of the second via is 4000 Å to 7000 Å.
5. 5 . The display substrate according to claim 1 , wherein a difference between the depth of the first via and the depth of the second via is less than or equal to 2000 Å.
6. 6 . The display substrate according to claim 1 , wherein the fourth insulation layer comprises a silicon oxide sub-layer and a silicon nitride sub-layer which are stacked, a thickness of the silicon nitride sub-layer is less than or equal to 1.5 times a thickness of the silicon oxide sub-layer.
7. 7 . The display substrate according to claim 2 , wherein a thickness of the first insulation layer is greater than or equal to 3 times a thickness of the second insulation layer.
8. 8 . The display substrate according to claim 1 , wherein a groove is provided on the base substrate, at least part of the second bottom gate electrode is disposed in the groove, at least part of the second active layer of the second transistor is disposed in the groove, and a second top gate electrode of the second transistor is disposed in the groove.
9. 9 . The display substrate according to claim 8 , wherein a depth of the groove is greater than or equal to 4000 Å, and a width of the groove is greater than or equal to 1.2 times a distance between a source region and a drain region of the second active layer in the second transistor.
10. 10 . A display apparatus, comprising the display substrate according to claim 1 .
11. 11 . A preparation method of a display substrate, comprising: forming a drive structure layer on a base substrate, wherein the drive structure layer comprises a first transistor and a second transistor arranged side by side, the first transistor comprises a low temperature poly silicon transistor, and the second transistor comprises an oxide transistor; the first transistor comprises a first bottom gate electrode simultaneously served as a shielding layer, the second transistor comprises a second bottom gate electrode simultaneously served as a shielding layer, and the first bottom gate electrode and the second bottom gate electrode are arranged in a same layer and simultaneously formed through a same patterning process; wherein the forming the drive structure layer on the base substrate comprises: forming a first conductive layer on the base substrate, wherein the first conductive layer comprises the first bottom gate electrode and the second bottom gate electrode, which are arranged in the same layer and simultaneously formed through the same patterning process; forming an active structure layer on the first conductive layer, wherein the active structure layer comprises a first active layer and a first top gate electrode of the first transistor, and a second active layer and a second top gate electrode of the second transistor; and forming a source drain structure layer on the active structure layer; wherein the source drain structure layer comprises a first source electrode and a first drain electrode of the first transistor, a first connection electrode, and a second source electrode and a second drain electrode of the second transistor, the first source electrode and the first drain electrode are connected with the first active layer through a first via, the second source electrode and the second drain electrode are connected with the second active layer through a second via, and the first connection electrode is connected with the first bottom gate electrode through a third via; when the first via, the second via, and the third via are formed, the fourth insulation layer, a third insulation layer, and a second insulation layer in the first via are etched away to expose surfaces of a source region and a drain region on both sides of the first active layer, and the first via is a low temperature poly silicon CNT-L via; the fourth insulation layer and the third insulation layer in the second via are etched away to expose surfaces of a source region and a drain region on both sides of the second active layer, and the second via is an oxide CNT-O via; the fourth insulation layer, the third insulation layer, the second insulation layer, and a first insulation layer in the third via are etched away to expose a surface of the first bottom gate electrode; and the first via, the second via, and the third via are formed simultaneously through a same patterning process.
12. 12 . The preparation method according to claim 11 , wherein the forming the drive structure layer on the base substrate further comprises: forming a base substrate, wherein the base substrate comprises a first flexible layer, a first barrier layer, a second flexible layer, and a second barrier layer which are stacked, a groove is provided on the second barrier layer, and a depth of the groove is greater than or equal to 4000 Å; wherein at least part of the second bottom gate electrode is disposed in the groove.
13. 13 . The preparation method according to claim 11 , wherein the forming the active structure layer on the first conductive layer comprises: forming the first insulation layer covering the first conductive layer, and the first active layer of the first transistor disposed on the first insulation layer; forming the second insulation layer covering the first active layer, and a first top gate electrode of the first transistor disposed on the second insulation layer; performing a doping treatment by taking the first top gate electrode as a shield; forming the second active layer of the second transistor on the second insulation layer; and forming the third insulation layer covering the first top gate electrode and the second active layer, and a second top gate electrode of the second transistor disposed on the third insulation layer.
14. 14 . The preparation method according to claim 11 , wherein the forming the active structure layer on the first conductive layer comprises: forming the first insulation layer covering the first conductive layer, and the first active layer of the first transistor disposed on the first insulation layer; forming the second insulation layer covering the first active layer, and a photoresist shielding pattern disposed on the second insulation layer; performing a doping treatment by taking the photoresist shielding pattern as a shield; forming the second active layer of the second transistor on the second insulation layer; and forming the third insulation layer covering a second semiconductor layer, and a first top gate electrode of the first transistor and a second top gate electrode of the second transistor disposed on the third insulation layer.
15. 15 . The preparation method according to claim 11 , wherein a depth of the first via is 5000 Å to 9000 Å, and a depth of the second via is 4000 Å to 7000 Å, and a difference between the depth of the first via and the depth of the second via is less than or equal to 2000 Å.
16. 16 . The display substrate according to claim 2 , wherein a groove is provided on the base substrate, at least part of the second bottom gate electrode is disposed in the groove, at least part of the second active layer of the second transistor is disposed in the groove, and a second top gate electrode of the second transistor is disposed in the groove.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application is a U.S. National Phase Entry of International Application No. PCT/CN2021/101857 having an international filing date of Jun. 23, 2021. The entire contents of the above-identified application are hereby incorporated by reference. TECHNICAL FIELD The present disclosure relates to, but is not limited to, the field of display technologies, and particularly to a display substrate, a preparation method thereof, and a display apparatus. BACKGROUND An Organic Light Emitting Diode (OLED) is an active light emitting display device, which has advantages of auto-luminescence, a wide angle of view, a high contrast ratio, low power consumption, an extremely high response speed, lightness and thinness, bendability, a low cost, etc. With constant development of display technologies, a flexible display apparatus (Flexible Display) using an OLED as a light emitting device and performing signal control by using a Thin Film Transistor (TFT for short) has become a mainstream product in the field of display at present. SUMMARY The following is a summary about subject matters described in the present disclosure in detail. The summary is not intended to limit a scope of protection of claims. In one aspect, the present disclosure provides a display substrate including a base substrate and a drive structure layer disposed on the base substrate, wherein the drive structure layer includes a first transistor and a second transistor arranged side by side, the first transistor includes a low temperature poly silicon transistor, and the second transistor includes an oxide transistor; the first transistor includes a first bottom gate electrode simultaneously served as a shielding layer, the second transistor includes a second bottom gate electrode simultaneously served as a shielding layer, and the first bottom gate electrode and the second bottom gate electrode are arranged in a same layer. In an exemplary implementation mode, the drive structure layer includes a first conductive layer disposed on the base substrate, an active structure layer disposed on a side of the first conductive layer away from the base substrate, and a source drain structure layer disposed on a side of the active structure layer away from the base substrate; the first conductive layer includes the first bottom gate electrode and the second bottom gate electrode arranged in the same layer In an exemplary implementation mode, the active structure layer includes: a first insulation layer covering the first conductive layer, a first active layer of the first transistor disposed on a side of the first insulation layer away from the base substrate, a second insulation layer covering the first active layer, a first top gate electrode of the first transistor disposed on a side of the second insulation layer away from the base substrate, a second active layer of the second transistor disposed on a side of the second insulation layer away from the base substrate, a third insulation layer covering the first gate top electrode and the second active layer, and a second top gate electrode of the second transistor disposed on a side of the third insulation layer away from the base substrate. In an exemplary implementation mode, the active structure layer includes: a first insulation layer covering the first conductive layer, a first active layer of the first transistor disposed on a side of the first insulation layer away from the base substrate, a second insulation layer covering the first active layer, a second active layer of the second transistor disposed on a side of the second insulation layer away from the base substrate, a third insulation layer covering the second active layer, and a first top gate electrode of the first transistor and a second top gate electrode of the second transistor disposed on a side of the third insulation layer away from the base substrate; the first top gate electrode and the second top gate electrode are arranged in a same layer. In an exemplary implementation mode, the source drain structure layer includes: a fourth insulation layer disposed on a side of the active structure layer away from the base substrate, a source drain metal layer disposed on the fourth insulation layer, wherein the source drain metal layer includes a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, and a first connection electrode, the first source electrode and the first drain electrode are connected with a first active layer of the first transistor through a first via, the second source electrode and the second drain electrode are connected with a second active layer of the second transistor through a second via, and the first connection electrode is connected with the first bottom gate electrode of the first transistor through a third via. In an exemplary implementation mode, a depth of the first via is 5000 Å to 9000 Å and a depth of the second via is