US-12628508-B2 - Display substrate, method for manufacturing same and display device

Abstract

Provided is a display substrate. The display substrate includes a base substrate which includes a first surface; a first transistor which includes a first active layer and a first gate insulative layer; a first insulative layer; and a second transistor which includes a second active layer and an orthographic projection of the second active layer on the first surface is staggered from an orthographic projection of the first active layer on the first surface.

Inventors

• Yuanzheng GUO
• Peng Huang
• Tao Gao

Assignees

• CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
• BOE TECHNOLOGY GROUP CO., LTD.

Dates

Publication Date

20260512

Application Date

20211012

Priority Date

20201127

Claims (18)

1. 1 . A display substrate, comprising: a base substrate, comprising a first surface; a first transistor, comprising a first active layer and a first gate insulative layer, the first active layer being disposed on the first surface of the base substrate, the first gate insulative layer being disposed on a side, distal from the first surface, of the first active layer and covering the first active layer; a first insulative layer, disposed on a side, distal from the first surface, of the first gate insulative layer and provided with a first opening running through the first insulative layer; and a second transistor, comprising a second active layer disposed in the first opening, an orthographic projection of the second active layer on the first surface being staggered from an orthographic projection of the first active layer on the first surface, the second active layer being made from an oxide semiconductor material, wherein the second active layer is disposed on the first gate insulative layer; wherein the first transistor further comprises: a first control electrode, a first electrode, and a second electrode; wherein the first control electrode is disposed on a side, distal from the first surface, of the first gate insulative layer, the first insulative layer covers the first control electrode; and the first electrode and the second electrode run through the first insulative layer and the first gate insulative layer, and are electrically connected to the first active layer; and the second transistor further comprises: a second gate insulative layer, a second control electrode, a second insulative layer, a third electrode, and a fourth electrode; wherein the second gate insulative layer and the second control electrode are sequentially stacked on the second active layer in a direction away from the first surface; the second insulative layer covers the second active layer, the second gate insulative layer, and the second control electrode; the third electrode and the fourth electrode run through the second insulative layer; the third electrode is electrically connected to the second active electrode and the first control electrode; and the fourth electrode is electrically connected to the second active layer; wherein the second gate insulative layer, the second control electrode, and the second insulative layer are all disposed in the first opening.
2. 2 . The display substrate according to claim 1 , wherein the first insulative layer is an organic layer, and a heat-resistant temperature of the first insulative layer is greater than 350° C.
3. 3 . The display substrate according to claim 2 , wherein the first insulative layer comprises a photosensitive polyimide layer.
4. 4 . The display substrate according to claim 1 , wherein a thickness of the first insulative layer in a direction perpendicular to the first surface is less than or equal to 3 μm.
5. 5 . The display substrate according to claim 1 , wherein the first insulative layer and the first gate insulative layer are provided with first via holes, and the first electrode and the second electrode are electrically connected to the first active layer via the different first via holes.
6. 6 . The display substrate according to claim 1 , wherein the second insulative layer wraps the second active layer, the second gate insulative layer, and the second control electrode; the second insulative layer is provided with second via holes; and the third electrode and the fourth electrode are electrically connected to the second active layer via the different second via holes.
7. 7 . The display substrate according to claim 6 , further comprising: a planarization layer disposed on a side, distal from the first surface, of the first insulative layer, and covering the first electrode, the second electrode, the third electrode, the fourth electrode, the second insulative layer and the first insulative layer; and an anode layer disposed on a side, distal from the first surface, of the planarization layer, and electrically connected to the second electrode; wherein an orthographic projection of the anode layer on the first surface is staggered from the orthographic projection of the second active layer on the first surface.
8. 8 . The display substrate according to claim 7 , wherein the orthographic projection of the first active layer on the first surface is within the orthographic projection of the anode layer on the first surface.
9. 9 . The display substrate according to claim 1 , wherein the first active layer is a low-temperature polysilicon (LTPS) layer.
10. 10 . The display substrate according to claim 1 , wherein the second active layer is an indium gallium zinc oxide (IGZO) semiconductor layer.
11. 11 . The display substrate according to claim 1 , wherein the base substrate is a polyimide (PI) substrate.
12. 12 . A method for manufacturing a display substrate, comprising: providing a base substrate having a first surface; forming a first active layer of a first transistor on a first surface of the base substrate; forming a first gate insulative layer of the first transistor on a side, distal from the first surface, of the first active layer, the first gate insulative layer covering the first active layer; forming a first insulative layer on a side, distal from the first surface, of the first gate insulative layer, the first insulative layer being provided with a first opening running through the first insulative layer; forming a second active layer of a second transistor in the first opening, the second active layer being made from an oxide semiconductor material, an orthographic projection of the second active layer on the first surface being staggered from an orthographic projection of the first active layer on the first surface, wherein the second active layer is disposed on the first gate insulative layer; wherein the first transistor further comprises: a first control electrode, a first electrode, and a second electrode; wherein the first control electrode is disposed on a side, distal from the first surface, of the first gate insulative layer, the first insulative layer covers the first control electrode; and the first electrode and the second electrode run through the first insulative layer and the first gate insulative layer, and are electrically connected to the first active layer; and the second transistor further comprises: a second gate insulative layer, a second control electrode, a second insulative layer, a third electrode, and a fourth electrode; wherein the second gate insulative layer and the second control electrode are sequentially stacked on the second active layer in a direction away from the first surface; the second insulative layer covers the second active layer, the second gate insulative layer, and the second control electrode; the third electrode and the fourth electrode run through the second insulative layer; the third electrode is electrically connected to the second active electrode and the first control electrode; and the fourth electrode is electrically connected to the second active layer; wherein the second gate insulative layer, the second control electrode, and the second insulative layer are all disposed in the first opening.
13. 13 . The method for manufacturing the display substrate according to claim 12 , further comprising: forming a third via hole in the first insulative layer to expose the first gate insulative layer; forming a fourth via hole in an exposed portion of the first gate insulative layer to expose the first active layer, the fourth via hole being communicated with the third via hole to form a first via hole; and forming a first electrode and a second electrode of the first transistor on a side, distal from the first surface, of the first insulative layer, the first electrode and the second electrode being electrically connected to the first active layer via different first via holes.
14. 14 . A display device, comprising a display substrate, wherein the display substrate comprises a base substrate, comprising a first surface; a first transistor, comprising a first active layer and a first gate insulative layer, the first active layer being disposed on the first surface of the base substrate, the first gate insulative layer being disposed on a side, distal from the first surface, of the first active layer and covering the first active layer; a first insulative layer, disposed on a side, distal from the first surface, of the first gate insulative layer and provided with a first opening running through the first insulative layer; and a second transistor, comprising a second active layer disposed in the first opening, an orthographic projection of the second active layer on the first surface being staggered from an orthographic projection of the first active layer on the first surface, the second active layer being made from an oxide semiconductor material, wherein the second active layer is disposed on the first gate insulative layer; wherein the first transistor further comprises: a first control electrode, a first electrode, and a second electrode; wherein the first control electrode is disposed on a side, distal from the first surface, of the first gate insulative layer, the first insulative layer covers the first control electrode; and the first electrode and the second electrode run through the first insulative layer and the first gate insulative layer, and are electrically connected to the first active layer; and the second transistor further comprises: a second gate insulative layer, a second control electrode, a second insulative layer, a third electrode, and a fourth electrode; wherein the second gate insulative laver and the second control electrode are sequentially stacked on the second active layer in a direction away from the first surface; the second insulative layer covers the second active layer, the second gate insulative layer, and the second control electrode; the third electrode and the fourth electrode run through the second insulative layer; the third electrode is electrically connected to the second active electrode and the first control electrode; and the fourth electrode is electrically connected to the second active layer; wherein the second gate insulative layer, the second control electrode, and the second insulative laver are all disposed in the first opening.
15. 15 . The display device according to claim 14 , wherein the first insulative layer is an organic layer, and a heat-resistant temperature of the first insulative layer is greater than 350° C.
16. 16 . The display device according to claim 15 , wherein the first insulative layer comprises a photosensitive polyimide layer.
17. 17 . The display device according to claim 14 , wherein a thickness of the first insulative layer in a direction perpendicular to the first surface is less than or equal to 3 μm.
18. 18 . The display device according to claim 14 , wherein the second active layer is an indium gallium zinc oxide (IGZO) semiconductor layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present disclosure is a U.S. national stage of the international application No. PCT/CN2021/123304, filed on Oct. 12, 2021, which claims priority to Chinese Patent Application No. 202011363144.5, filed on Nov. 27, 2020 and entitled “DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE.” the disclosures of which are incorporated herein by reference in their entireties. TECHNICAL FIELD The present disclosure relates to the field of displays, and in particular relates to a display substrate, a method for manufacturing the same and a display device. BACKGROUND A flexible display panel, which has attracted more and more attention because of its foldability, includes a display substrate having a plurality of pixel regions arranged in an array, one organic light-emitting diode (OLED) and one pixel circuit are arranged in each pixel region, and the pixel circuit is configured to control the connected light-emitting diode to emit light. SUMMARY Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same and a display device. The technical solutions are described as below. According to some embodiments of the present disclosure, the present disclosure provides a display substrate. The display substrate includes: a base substrate, including a first surface;a first transistor, including a first active layer and a first gate insulative layer, the first active layer being disposed on the first surface of the base substrate, the first gate insulative layer being disposed on a side, distal from the first surface, of the first active layer, and covering the first active layer;a first insulative layer, disposed on a side, distal from the first surface, of the first gate insulative layer and provided with a first opening running through the first insulative layer; anda second transistor, including a second active layer disposed in the first opening, an orthographic projection of the second active layer on the first surface being staggered from an orthographic projection of the first active layer on the first surface, the second active layer being made from an oxide semiconductor material. In some embodiments of the present disclosure, a heat-resistant temperature of the first insulative layer is greater than 350° C. In some embodiments of the present disclosure, the first insulative layer includes a photosensitive polyimide (PSPI) layer. In some embodiments of the present disclosure, a thickness of the first insulative layer in a direction perpendicular to the first surface is less than or equal to 3 μm. In some embodiments of the present disclosure, the first transistor further includes a first control electrode, a first electrode, and a second electrode; wherein the first control electrode is disposed on a side, distal from the first surface, of the first gate insulative layer; the first insulative layer covers the first control electrode; and the first electrode and the second electrode run through the first insulative layer and the first gate insulative layer, and are electrically connected to the first active layer; and the second transistor further includes a second gate insulative layer, a second control electrode, a second insulative layer, a third electrode, and a fourth electrode; wherein the second gate insulative layer and the second control electrode are sequentially stacked on the second active layer in a direction away from the first surface; the second insulative layer covers the second active layer, the second gate insulative layer and the second control electrode; the third electrode and the fourth electrode run through the second insulative layer; the third electrode is electrically connected to the second active electrode and the first control electrode; and the fourth electrode is electrically connected to the second active layer;wherein the second gate insulative layer, the second control electrode, and the second insulative layer are all disposed in the first opening. In some embodiments of the present disclosure, the first insulative layer and the first gate insulative layer are provided with first via holes, wherein the first electrode and the second electrode are electrically connected to the first active layer via the different first via holes. In some embodiments of the present disclosure, the second insulative layer wraps the second active layer, the second gate insulative layer, and the second control electrode; the second insulative layer is provided with second via holes; and the third electrode and the fourth electrode are electrically connected to the second active layer via the different second via holes. In some embodiments of the present disclosure, the display substrate further includes: a planarization layer disposed on a side, distal from the first surface, of the first insulative layer and covering the first electrode, the second electrode, the third electrode, the fourth electrode, t