US-12628567-B2 - Method for fabricating semiconductor device

US12628567B2US 12628567 B2US12628567 B2US 12628567B2US-12628567-B2

Abstract

A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a substrate, forming a spin orbit torque (SOT) layer on the MTJ, forming an inter-metal dielectric (IMD) layer around the MTJ and the SOT layer, forming a first hard mask on the IMD layer, forming a semiconductor layer on the first hard mask, and then patterning the first hard mask.

Inventors

Hung-Yi Wu
Jia-Rong Wu
YU-HSIANG LIN
Yi-Wen Chen
Kun-Sheng Yang

Assignees

UNITED MICROELECTRONICS CORP.

Dates

Publication Date: 20260512
Application Date: 20220324
Priority Date: 20220224

Claims (9)

1 . A method for fabricating a semiconductor device, comprising: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a spin orbit torque (SOT) layer on the MTJ stack; forming a third hard mask directly on the SOT layer; patterning the third hard mask, the SOT layer, and the MTJ stack to form a MTJ, wherein sidewalls of the third hard mask, the SOT layer, and the MTJ are aligned; forming a spacer adjacent to two sides of the third hard mask, the SOT layer, and the MTJ; forming an inter-metal dielectric (IMD) layer around the MTJ and the SOT layer, wherein top surfaces of the IMD layer and the third hard mask are coplanar; forming a first hard mask on the IMD layer and the MTJ, wherein a bottom surface of the first hard mask is even with top surfaces of the IMD layer, the spacer, and the third hard mask; forming a semiconductor layer on and directly contacting a top surface of the first hard mask, wherein the semiconductor layer overlaps the MTJ and the first IMD entirely and a bottom surface of the semiconductor layer is higher than top surfaces of IMD layer, the spacer, and the third hard mask; and patterning the first hard mask.
2 . The method of claim 1 , further comprising: forming the spacer adjacent to the MTJ and the SOT layer; forming the IMD layer around the spacer; forming a second hard mask on the semiconductor layer; patterning the semiconductor layer; using the second hard mask to pattern the first hard mask; removing the second hard mask; and removing the semiconductor layer.
3 . The method of claim 2 , further comprising conducting a dry etching process to pattern the semiconductor layer.
4 . The method of claim 2 , further comprising conducting a wet etching process to remove the first hard mask.
5 . The method of claim 2 , further comprising conducting a wet etching process to remove the second hard mask.
6 . The method of claim 2 , further comprising conducting a wet etching process to remove the semiconductor layer.
7 . The method of claim 2 , wherein the second hard mask comprises a dielectric layer.
8 . The method of claim 1 , wherein the first hard mask comprises metal nitride.
9 . The method of claim 1 , wherein the semiconductor layer comprises polysilicon.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention relates to a method for fabricating semiconductor device, and more particularly to a method for fabricating magnetoresistive random access memory (MRAM). 2. Description of the Prior Art Magnetoresistance (MR) effect has been known as a kind of effect caused by altering the resistance of a material through variation of outside magnetic field. The physical definition of such effect is defined as a variation in resistance obtained by dividing a difference in resistance under no magnetic interference by the original resistance. Currently, MR effect has been successfully utilized in production of hard disks thereby having important commercial values. Moreover, the characterization of utilizing GMR materials to generate different resistance under different magnetized states could also be used to fabricate MRAM devices, which typically has the advantage of keeping stored data even when the device is not connected to an electrical source. The aforementioned MR effect has also been used in magnetic field sensor areas including but not limited to for example electronic compass components used in global positioning system (GPS) of cellular phones for providing information regarding moving location to users. Currently, various magnetic field sensor technologies such as anisotropic magnetoresistance (AMR) sensors, GMR sensors, magnetic tunneling junction (MTJ) sensors have been widely developed in the market. Nevertheless, most of these products still pose numerous shortcomings such as high chip area, high cost, high power consumption, limited sensibility, and easily affected by temperature variation and how to come up with an improved device to resolve these issues has become an important task in this field. SUMMARY OF THE INVENTION According to an embodiment of the present invention, a method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a substrate, forming a spin orbit torque (SOT) layer on the MTJ, forming an inter-metal dielectric (IMD) layer around the MTJ and the SOT layer, forming a first hard mask on the IMD layer, forming a semiconductor layer on the first hard mask, and then patterning the first hard mask. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1-11 illustrate a method for fabricating a MRAM device according to an embodiment of the present invention. DETAILED DESCRIPTION Referring to FIGS. 1-11, FIGS. 1-11 illustrate a method for fabricating a MRAM device according to an embodiment of the present invention. As shown in FIG. 1, a substrate 12 made of semiconductor material is first provided, in which the semiconductor material could be selected from the group consisting of silicon (Si), germanium (Ge), Si—Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs), and a MRAM region 14 and a logic region 16 are defined on the substrate 12. Active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and interlayer dielectric (ILD) layer 18 could also be formed on top of the substrate 12. More specifically, planar MOS transistors or non-planar (such as FinFETs) MOS transistors could be formed on the substrate 12, in which the MOS transistors could include transistor elements such as gate structures (for example metal gates) and source/drain region, spacer, epitaxial layer, and contact etch stop layer (CESL). The ILD layer 18 could be formed on the substrate 12 to cover the MOS transistors, and a plurality of contact plugs could be formed in the ILD layer 18 to electrically connect to the gate structure and/or source/drain region of MOS transistors. Since the fabrication of planar or non-planar transistors and ILD layer is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. Next, metal interconnect structures 20, 22 are sequentially formed on the ILD layer 18 on the MRAM region 14 and the logic region 16 to electrically connect the aforementioned contact plugs, in which the metal interconnect structure 20 includes an inter-metal dielectric (IMD) layer 24 and metal interconnections 26 embedded in the IMD layer 24, and the metal interconnect structure 22 includes a stop layer 28, an IMD layer 30, and metal interconnections 32 embedded in the stop layer 28 and the IMD layer 30. In this embodiment, each of the metal interconnections 26 from the metal interconnect structure 20 preferably includes a trench conductor and the metal interconnection 32 from the metal interconnect structure 22 on the MRAM region 14 includes a via conductor. Preferably, each of the metal interconnections 26, 32 from the metal interconnect structures 20, 22 c