US-12628568-B2 - Magnetoresistive random access memory and method for fabricating the same

US12628568B2US 12628568 B2US12628568 B2US 12628568B2US-12628568-B2

Abstract

A method for fabricating a semiconductor device includes the steps of providing a substrate comprising a magnetic random access memory (MRAM) region and a logic region, forming a first magnetic tunneling junction (MTJ) on the MRAM region, forming a first inter-metal dielectric (IMD) layer around the first MTJ, and then forming a first metal interconnection extending from the MRAM region to the logic region on the first MTJ. Preferably, the first metal interconnection on the MRAM region and the first metal interconnection on the logic region have different heights.

Inventors

Hui-Lin WANG
Ching-Hua Hsu
Che-wei Chang
Chen-Yi Weng

Assignees

UNITED MICROELECTRONICS CORP.

Dates

Publication Date: 20260512
Application Date: 20230502
Priority Date: 20230330

Claims (16)

1 . A method for fabricating a semiconductor device, comprising: providing a substrate comprising a magnetic random access memory (MRAM) region and a logic region; forming a first magnetic tunneling junction (MTJ) on the MRAM region; forming a first inter-metal dielectric (IMD) layer around the first MTJ; and forming a first metal interconnection extending continuously from the MRAM region to the logic region on the first MTJ, wherein the first metal interconnection on the MRAM region and the first metal interconnection on the logic region comprise same element and different heights.
2 . The method of claim 1 , further comprising: forming the first MTJ and a second MTJ on the MRAM region; forming a cap layer on the first MTJ and the second MTJ; forming a dielectric layer on the cap layer; patterning the dielectric layer and the cap layer; and forming the first IMD layer on the dielectric layer; forming the first metal interconnection on the first MTJ and the second MTJ and the first metal interconnection on the logic region; forming a stop layer on the first metal interconnection; forming a second IMD layer on the stop layer; and forming a second metal interconnection extending from the MRAM region to the logic region in the second IMD layer and connected to the first metal interconnection on the MRAM region and the first metal interconnection on the logic region.
3 . The method of claim 2 , wherein the second metal interconnection on the MRAM region and the second metal interconnection on the logic region comprise same height.
4 . The method of claim 2 , wherein the dielectric layer is between the first MTJ and the second MTJ.
5 . The method of claim 4 , wherein a top surface of the dielectric layer comprises a V-shape.
6 . The method of claim 1 , wherein top surfaces of the first metal interconnection on the MRAM region and the first metal interconnection on the logic region are coplanar.
7 . The method of claim 1 , wherein a top surface of the first metal interconnection on the logic region is lower than a top surface of the first metal interconnection on the MRAM region.
8 . The method of claim 1 , wherein a height of the first metal interconnection on the MRAM region is less than a height of the first metal interconnection on the logic region.
9 . A semiconductor device, comprising: a substrate comprising a magnetic random access memory (MRAM) region and a logic region; a first magnetic tunneling junction (MTJ) on the MRAM region; a first inter-metal dielectric (IMD) layer around the first MTJ; and a first metal interconnection extending continuously from the MRAM region to the logic region on the first MTJ, wherein the first metal interconnection on the MRAM region and the first metal interconnection on the logic region comprise same element and different heights.
10 . The semiconductor device of claim 9 , further comprising: a second MTJ on the MRAM region; a cap layer adjacent to the first MTJ and the second MTJ; a dielectric layer around the cap layer; the first IMD layer around the dielectric layer; the first metal interconnection on the first MTJ and the second MTJ; a stop layer on the first metal interconnection; a second IMD layer on the stop layer; and a second metal interconnection extending from the MRAM region to the logic region in the second IMD layer and connected to the first metal interconnection on the MRAM region and the first metal interconnection on the logic region.
11 . The semiconductor device of claim 10 , wherein the second metal interconnection on the MRAM region and the second metal interconnection on the logic region comprise same height.
12 . The semiconductor device of claim 10 , wherein the dielectric layer is between the first MTJ and the second MTJ.
13 . The semiconductor device of claim 12 , wherein a top surface of the dielectric layer comprises a V-shape.
14 . The semiconductor device of claim 9 , wherein top surfaces of the first metal interconnection on the MRAM region and the first metal interconnection on the logic region are coplanar.
15 . The semiconductor device of claim 9 , wherein a top surface of the first metal interconnection on the logic region is lower than a top surface of the first metal interconnection on the MRAM region.
16 . The semiconductor device of claim 9 , wherein a height of the first metal interconnection on the MRAM region is less than a height of the first metal interconnection on the logic region.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention relates to a method for fabricating semiconductor device, and more particularly to a method for fabricating a magnetoresistive random access memory (MRAM). 2. Description of the Prior Art Magnetoresistance (MR) effect has been known as a kind of effect caused by altering the resistance of a material through variation of outside magnetic field. The physical definition of such effect is defined as a variation in resistance obtained by dividing a difference in resistance under no magnetic interference by the original resistance. Currently, MR effect has been successfully utilized in production of hard disks thereby having important commercial values. Moreover, the characterization of utilizing GMR materials to generate different resistance under different magnetized states could also be used to fabricate MRAM devices, which typically has the advantage of keeping stored data even when the device is not connected to an electrical source. The aforementioned MR effect has also been used in magnetic field sensor areas including but not limited to for example electronic compass components used in global positioning system (GPS) of cellular phones for providing information regarding moving location to users. Currently, various magnetic field sensor technologies such as anisotropic magnetoresistance (AMR) sensors, GMR sensors, magnetic tunneling junction (MTJ) sensors have been widely developed in the market. Nevertheless, most of these products still pose numerous shortcomings such as high chip area, high cost, high power consumption, limited sensibility, and easily affected by temperature variation and how to come up with an improved device to resolve these issues has become an important task in this field. SUMMARY OF THE INVENTION According to an embodiment of the present invention, a method for fabricating a semiconductor device includes the steps of providing a substrate comprising a magnetic random access memory (MRAM) region and a logic region, forming a first magnetic tunneling junction (MTJ) on the MRAM region, forming a first inter-metal dielectric (IMD) layer around the first MTJ, and then forming a first metal interconnection extending from the MRAM region to the logic region on the first MTJ. Preferably, the first metal interconnection on the MRAM region and the first metal interconnection on the logic region have different heights. According to another aspect of the present invention, a semiconductor device includes a substrate including a magnetic random access memory (MRAM) region and a logic region, a first magnetic tunneling junction (MTJ) on the MRAM region, a first inter-metal dielectric (IMD) layer around the first MTJ, and a first metal interconnection extending from the MRAM region to the logic region on the first MTJ. Preferably, the first metal interconnection on the MRAM region and the first metal interconnection on the logic region have different heights. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1-5 illustrate a method for fabricating a MRAM device according to an embodiment of the present invention. FIG. 6 illustrates a structural view of a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION Referring to FIGS. 1-5, FIGS. 1-5 illustrate a method for fabricating a MRAM device according to an embodiment of the present invention. As shown in FIG. 1, a substrate 12 made of semiconductor material is first provided, in which the semiconductor material could be selected from the group consisting of silicon (Si), germanium (Ge), Si—Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs), and a MRAM region 14 and a logic region 16 are defined on the substrate 12. Active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and interlayer dielectric (ILD) layer 18 could also be formed on top of the substrate 12. More specifically, planar MOS transistors or non-planar (such as FinFETs) MOS transistors could be formed on the substrate 12, in which the MOS transistors could include transistor elements such as gate structures (for example metal gates) and source/drain region, spacer, epitaxial layer, and contact etch stop layer (CESL). The ILD layer 18 could be formed on the substrate 12 to cover the MOS transistors, and a plurality of contact plugs could be formed in the ILD layer 18 to electrically connect to the gate structure and/or source/drain region of MOS transistors. Since the fabrication of planar or non-planar transistors and ILD layer is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. Next, metal interconnect structures 20,