US-12628570-B2 - Beveled magneto-resistive random access memory pillar structure

US12628570B2US 12628570 B2US12628570 B2US 12628570B2US-12628570-B2

Abstract

A memory device includes a magnetic tunnel junction pillar located between, and electrically connected to, a bottom electrode and a top electrode. The magnetic tunnel junction pillar is composed of a plurality of device layers vertically stacked above the bottom electrode. Each of the plurality of device layers, the top electrode, and the bottom electrode is formed at a first bevel angle. A bottommost portion of each of the plurality of device layers in the magnetic tunnel junction pillar has a width that is greater than a width of a topmost portion of each preceding device layer. An encapsulation layer is disposed along opposite sidewalls of the top electrode, opposite sidewalls of the bottom electrode, and opposite sidewalls of each of the plurality of device layers.

Inventors

Oscar van der Straten
Chih-Chao Yang
Praneet Adusumilli

Assignees

INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date: 20260512
Application Date: 20220624

Claims (16)

1 . A memory device, comprising: a magnetic tunnel junction pillar located between, and electrically connected to, a bottom electrode and a top electrode, the magnetic tunnel junction pillar including a plurality of device layers vertically stacked above the bottom electrode, each of the plurality of device layers, the top electrode, and the bottom electrode being at a first bevel angle; a bottommost portion of each of the plurality of device layers in the magnetic tunnel junction pillar having a width that is greater than a width of a topmost portion of each preceding device layer; and an encapsulation layer disposed along opposite sidewalls of the top electrode, opposite sidewalls of the bottom electrode, and opposite sidewalls of each of the plurality of device layers, wherein the plurality of device layers further comprises: a magnetic reference layer disposed above the bottom electrode, the magnetic reference layer including first beveled sidewalls comprising a first positive taper profile, a tunnel barrier layer disposed above the magnetic reference layer, the tunnel barrier layer including second beveled sidewalls comprising a second positive taper profile, and a magnetic free layer disposed above the tunnel barrier layer, the magnetic free layer including third beveled sidewalls comprising a third positive taper profile, and wherein the bottommost portion of each of the plurality of device layers being greater than the topmost portion of each preceding device layer further comprises: a bottommost portion of the magnetic reference layer being greater than a topmost portion of the bottom electrode, a bottommost portion of the tunnel barrier layer being greater than a topmost portion of the magnetic reference layer, a bottommost portion of the magnetic free layer being greater than a topmost portion of the tunnel barrier layer, and a bottommost portion of the top electrode being greater than a topmost portion of the magnetic free layer.
2 . The memory device of claim 1 , wherein the top electrode includes fourth beveled sidewalls comprising a fourth positive taper profile, and the bottom electrode includes fifth beveled sidewalls comprising a fifth positive taper profile.
3 . The memory device of claim 1 , wherein the encapsulation layer disposed along opposite sidewalls of the top electrode and opposite sidewalls of the bottom electrode includes at least one of a first nitride material and a metal-oxide material.
4 . The memory device of claim 3 , wherein the first nitride material comprises SiN, and the metal-oxide material comprises at least one of RuO 2 and IrO 2 .
5 . The memory device of claim 1 , wherein the encapsulation layer disposed along the opposite sidewalls of each of the plurality of device layers comprises a second nitride material disposed along opposite sidewalls of the magnetic reference layer, opposite sidewalls of the tunnel barrier layer, and opposite sidewalls of the magnetic free layer.
6 . The memory device of claim 5 , wherein the second nitride material comprises SiN.
7 . The memory device of claim 5 , wherein the encapsulation layer disposed along opposite sidewalls of each of the plurality of device layers comprises an oxynitride material disposed along the opposite sidewalls of the magnetic reference layer, and the second nitride material disposed along the opposite sidewalls of the tunnel barrier layer, and the opposite sidewalls of the magnetic free layer.
8 . The memory device of claim 7 , wherein the oxynitride material comprises AlON.
9 . A method of forming a memory device, comprising: forming a magnetic tunnel junction pillar between, and electrically connected to, a bottom electrode and a top electrode, the magnetic tunnel junction pillar including a plurality of device layers vertically stacked above the bottom electrode, each of the plurality of device layers, the top electrode, and the bottom electrode being at a first bevel angle, wherein a bottommost portion of each of the plurality of device layers in the magnetic tunnel junction pillar has a width that is greater than a width of a topmost portion of each preceding device layer; and forming an encapsulation layer along opposite sidewalls of the top electrode, opposite sidewalls of the bottom electrode, and opposite sidewalls of each of the plurality of device layers, wherein forming the magnetic tunnel junction pillar including the plurality of device layers further comprises: forming a magnetic reference layer above the bottom electrode, the magnetic reference layer including first beveled sidewalls comprising a first positive taper profile; forming a tunnel barrier layer above the magnetic reference layer, the tunnel barrier layer including second beveled sidewalls comprising a second positive taper profile; and forming a magnetic free layer above the tunnel barrier layer, the magnetic free layer including third beveled sidewalls comprising a third positive taper profile, and wherein the bottommost portion of each of the plurality of device layers being greater than the topmost portion of each preceding device layer further comprises: a bottommost portion of the magnetic reference layer being greater than a topmost portion of the bottom electrode, a bottommost portion of the tunnel barrier layer being greater than a topmost portion of the magnetic reference layer, a bottommost portion of the magnetic free layer being greater than a topmost portion of the tunnel barrier layer, and a bottommost portion of the top electrode being greater than a topmost portion of the magnetic free layer.
10 . The method of claim 9 , wherein the top electrode includes fourth beveled sidewalls comprising a fourth positive taper profile, and the bottom electrode includes fifth beveled sidewalls comprising a fifth positive taper profile.
11 . The method of claim 9 , wherein the encapsulation layer along opposite sidewalls of the top electrode and the opposite sidewalls of the bottom electrode comprises at least one of a first nitride material and a metal-oxide material.
12 . The method of claim 11 , wherein the first nitride material comprises SiN, and the metal-oxide material comprises at least one of RuO 2 and IrO 2 .
13 . The method of claim 9 , wherein the encapsulation layer along the opposite sidewalls of each of the plurality of device layers comprises a second nitride material disposed along opposite sidewalls of the magnetic reference layer, opposite sidewalls of the tunnel barrier layer, and opposite sidewalls of the magnetic free layer.
14 . The method of claim 13 , wherein the second nitride material comprises SiN.
15 . The method of claim 13 , wherein the encapsulation layer along opposite sidewalls of each of the plurality of device layers comprises an oxynitride material along the opposite sidewalls of the magnetic reference layer, and the second nitride material along opposite sidewalls of the tunnel barrier layer, and the opposite sidewalls of the magnetic free layer.
16 . The method of claim 15 , wherein the oxynitride material comprises AlON.

Description

BACKGROUND The present invention generally relates to the field of magnetic storage devices, and more particularly to high performance magneto-resistive random access memory devices. Magneto-resistive random access memory (MRAM) is a non-volatile random access memory technology in which data is stored by magnetic storage elements. These magnetic storage elements are typically formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin dielectric layer, i.e., the tunnel barrier. One of the two plates is a permanent magnet set to a particular polarity; the other plate's magnetization can be changed to match that of an external field to store memory. Such configuration is known as a magnetic tunnel junction (MTJ) pillar. For high performance MRAM devices based on perpendicular MTJ pillars, well-defined interfaces and interface control are essential. Embedded MTJ pillar structures are usually formed by patterning of blanket MTJ stacks. After MTJ stack patterning, the inter-pillar spaces are filled with an interlevel dielectric (ILD) to enable connection to back-end-of-line (BEOL) wiring by a top contact level. However, voids may form in the ILD between top electrodes and top contact metals. During deposition of the top contact material, the contact material may fill the voids resulting in electric shorts. Thus, there is a need for improved designs and techniques that can prevent voids during ILD deposition. SUMMARY According to an embodiment of the present disclosure, a memory device includes a magnetic tunnel junction pillar located between, and electrically connected to, a bottom electrode and a top electrode, the magnetic tunnel junction pillar including a plurality of device layers vertically stacked above the bottom electrode, each of the plurality of device layers, the top electrode, and the bottom electrode being at a first bevel angle, a bottommost portion of each of the plurality of device layers in the magnetic tunnel junction pillar having a width that is greater than a width of a topmost portion of each preceding device layer, and an encapsulation layer disposed along opposite sidewalls of the top electrode, opposite sidewalls of the bottom electrode, and opposite sidewalls of each of the plurality of device layers. According to another embodiment of the present disclosure, a method of forming a memory device, includes forming a magnetic tunnel junction pillar between, and electrically connected to, a bottom electrode and a top electrode, the magnetic tunnel junction pillar including a plurality of device layers vertically stacked above the bottom electrode, each of the plurality of device layers, the top electrode, and the bottom electrode being at a first bevel angle, a bottommost portion of each of the plurality of device layers in the magnetic tunnel junction pillar having a width that is greater than a width of a topmost portion of each preceding device layer, and forming an encapsulation layer along opposite sidewalls of the top electrode, opposite sidewalls of the bottom electrode, and opposite sidewalls of each of the plurality of device layers. BRIEF DESCRIPTION OF THE DRAWINGS The following detailed description, given by way of example and not intended to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, in which: FIG. 1 is a cross-sectional view of a memory device at an intermediate step during a semiconductor manufacturing process, according to an embodiment of the present disclosure; FIG. 2 is a cross-sectional view of the memory device after forming a first conductive material, according to an embodiment of the present disclosure; FIG. 3 is a cross-sectional view of the memory device after forming a first hardmask layer and hardmask patterning, according to an embodiment of the present disclosure; FIG. 4 is a cross-sectional view of the memory device after etching the first conductive material to form a bottom electrode, according to an embodiment of the present disclosure; FIG. 5 is a cross-sectional view of the memory device after removing the first hardmask layer, according to an embodiment of the present disclosure; FIG. 6 is a cross-sectional view of the memory device after forming a first encapsulation layer, according to an embodiment of the present disclosure; FIG. 7 is a cross-sectional view of the memory device after etching the first encapsulation layer, according to an embodiment of the present disclosure; FIG. 8 is a cross-sectional view of the memory device after forming an interlevel dielectric layer, according to an embodiment of the present disclosure; FIG. 9 is a cross-sectional view of the memory device after planarizing the interlevel dielectric layer, according to an embodiment of the present disclosure; FIG. 10 is a cross-sectional view of the memory device after depositing a magnetic reference layer, according to an embodiment of the present disclosure; FIG. 11 is a cr