US-12628571-B2 - Magnetoresistive memory device and integrated memory circuit

Abstract

A magnetoresistive memory device and an integrated memory circuit are provided. The magnetoresistive memory device includes a magnetic tunneling junction (MTJ) and a composite spin orbit torque (SOT) channel in contact with a terminal of the MTJ. The SOT channel includes: a first channel layer, configured to convert a portion of a charge current into an orbital current based on orbital Hall effect; and a second channel layer, covering the first channel layer, and configured to convert a portion of the charge current into a first spin current based on spin Hall effect, and to convert the orbital current to a second spin current.

Inventors

• Ming-Yuan Song
• Chi-Feng Pai
• Xinyu Bao
• Chen-Yu Hu

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260512

Application Date

20231011

Claims (20)

1. 1 . A magnetoresistive memory device, comprising: a magnetic tunneling junction (MTJ), comprising a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer; and a composite spin orbit torque (SOT) channel, in contact with a terminal of the MTJ, and comprising: a first channel layer, configured to convert a portion of a charge current into an orbital current based on orbital Hall effect; and a second channel layer, covering the first channel layer, and configured to convert a portion of the charge current into a first spin current based on spin Hall effect, and to convert the orbital current to a second spin current.
2. 2 . The magnetoresistive memory device according to claim 1 , wherein the first and second spin currents are identical in terms of direction.
3. 3 . The magnetoresistive memory device according to claim 1 , wherein the second channel layer lies in between the first channel layer and the MTJ.
4. 4 . The magnetoresistive memory device according to claim 1 , wherein the first channel layer is formed of chromium, and the second channel layer is formed of tungsten.
5. 5 . The magnetoresistive memory device according to claim 1 , wherein the first channel layer is formed by one of chromium, vanadium, manganese and titanium, and the second channel layer is formed by one of tungsten, nickel, platinum, tantalum and gold.
6. 6 . The magnetoresistive memory device according to claim 1 , wherein an electrical resistivity of the first channel layer ranges from 100 μΩ·cm to 1400 μΩ·cm.
7. 7 . The magnetoresistive memory device according to claim 1 , wherein a thickness of the first channel layer ranges from 0.2 nm to 10 nm.
8. 8 . The magnetoresistive memory device according to claim 1 , wherein a thickness of the second channel layer ranges from 0.5 nm to 5 nm.
9. 9 . The magnetoresistive memory device according to claim 1 , wherein a total thickness of the composite SOT channel ranges from 0.7 nm to 15 nm.
10. 10 . A magnetoresistive memory device, comprising: a magnetic tunneling junction (MTJ), comprising a free layer, a reference layer over the free layer and a barrier layer lying between the free layer and the reference layer; and a composite spin orbit torque (SOT) channel, in contact with a terminal of the MTJ from below the MTJ, and comprising alternately stacked first channel layers and second channel layers, wherein each first channel layer is covered by one of the second channel layers, each first channel layer is configured to convert a portion of a charge current into an orbital current based on orbital Hall effect, and each second channel layer is configured to convert a portion of the charge current into a first spin current based on spin Hall effect, and to convert the orbital current generated by an underlying one of the first channel layers to a second spin current.
11. 11 . The magnetoresistive memory device according to claim 10 , wherein the composite SOT channel comprises two to eight film pairs, each comprising one of the first channel layers and one of the second channel layers.
12. 12 . The magnetoresistive memory device according to claim 10 , wherein a total thickness of the composite SOT channel ranges from 0.7 nm to 20 nm.
13. 13 . The magnetoresistive memory device according to claim 10 , wherein the first channel layers are identical with one another in terms of material, and the second channel layers are identical with one another in terms of material.
14. 14 . The magnetoresistive memory device according to claim 10 , wherein a material for forming at least one of the first channel layers is different from a material for forming others of the first channel layers.
15. 15 . The magnetoresistive memory device according to claim 10 , wherein a material for forming at least one of the second channel layers is different from a material for forming others of the second channel layers.
16. 16 . An integrated memory circuit, comprising: memory cells, arranged along rows and columns, and each comprising: a magnetic tunneling junction (MTJ); a composite spin orbit torque (SOT) channel, in contact with a first terminal of the MTJ, and comprising a first channel layer and a second channel layer stacked on the first channel layer, wherein the first channel layer is configured to convert a portion of a charge current into a first orbital current based on orbital Hall effect, and the second channel layer is configured to convert a portion of the charge current into a first spin current based on spin Hall effect, and to convert the first orbital current to a second spin current; a first access selector, coupled to a first edge region of the SOT channel; and a second access selector, coupled to a second edge region of the SOT channel or a second terminal of the MTJ.
17. 17 . The integrated memory circuit according to claim 16 , wherein the composite SOT channel in each memory cell further comprises: a third channel layer, configured to convert a portion of the charge current into a second orbital current based on orbital Hall effect; and a fourth channel layer, configured to convert a portion of the charge current into a third spin current, and to convert the second orbital current to a fourth spin current.
18. 18 . The integrated memory circuit according to claim 16 , wherein the first and second access selectors are respectively a three-terminal transistor, and the second access selector is coupled to the second edge region of the SOT channel.
19. 19 . The integrated memory circuit according to claim 16 , wherein the first and second access selectors are respectively a three-terminal transistor, and the second access selector is coupled to the second terminal of the MTJ.
20. 20 . The integrated memory circuit according to claim 16 , wherein the first and second access selectors are respectively a dual-terminal selector, and the second access selector is coupled to the second terminal of the MTJ 120 .

Description

BACKGROUND Magnetoresistive random access memory (MRAM) is one of the leading candidates for next-generation memory technologies that aim to surpass the performance of various existing memories. MRAM offers comparable performance to volatile static random access memory (SRAM) and comparable density with lower power consumption to volatile dynamic random access memory (DRAM). As compared to non-volatile flash memory, MRAM offers much faster access speed and suffers minimal degradation over time. Spin orbit torque MRAM (SOT-MRAM) is a type of MRAM. As compared to spin transfer torque MRAM (STT-MRAM), which is another type of MRAM, SOT-MRAM offers better performance in terms of speed and endurance. Nevertheless, further reducing switching energy of SOT-MRAM is limited. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A is a schematic cross-sectional view illustrating a magnetoresistive memory device, according to some embodiments of the present disclosure. FIG. 1B is a schematic diagram illustrating a charge-to-spin conversion process implemented by the SOT channel in the magnetoresistive memory device shown in FIG. 1A. FIG. 2 is a schematic cross-sectional view illustrating a magnetoresistive memory device, according to some embodiments of the present disclosure. FIG. 3 is a bar graph showing respective power density and respective switching efficiency of the magnetoresistive memory devices shown in FIG. 1A and FIG. 2 as well as a single spin Hall electrode (SHE) magnetoresistive memory device. FIG. 4A is a circuit diagram schematically illustrating a memory integrated circuit, according to some embodiments of the present disclosure. FIG. 4B illustrates a write path in a selected memory cell in the memory integrated circuit as shown in FIG. 4A. FIG. 4C illustrates a read path in a selected memory cell in the memory integrated circuit as shown in FIG. 4A. FIG. 4D is a schematic cross-sectional view illustrating one of the memory cells shown in FIG. 4A. FIG. 5A is a circuit diagram schematically illustrating a memory integrated circuit, according to some embodiments of the present disclosure. FIG. 5B is a schematic cross-sectional view illustrating one of the memory cells shown in FIG. 5A. FIG. 6A is a circuit diagram schematically illustrating a memory integrated circuit, according to some embodiments of the present disclosure. FIG. 6B is a schematic cross-sectional view illustrating one of the memory cells shown in FIG. 6A. DETAILED DESCRIPTION The following disclosure provides many different embodiments or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. FIG. 1A is a schematic cross-sectional view illustrating a magnetoresistive memory device 100, according to some embodiments of the present disclosure. Referring to FIG. 1A, the magnetoresistive memory device 100 includes a spin orbit torque (SOT) channel 110 and a magnetic tunneling junction (MTJ) 120 standing on top of the SOT channel 110. The MTJ 120 is functioned as a storage element, whereas the SOT channel 110 is configured to induce SOT in the MTJ 120, in order to program the MTJ 120. Specifically, magnetization orientations of ferromagnetic layers