US-12628572-B2 - Quantum device comprising first connection portions within deformation suppression region defined by second connection portions

US12628572B2US 12628572 B2US12628572 B2US 12628572B2US-12628572-B2

Abstract

A quantum device includes a chip including a superconducting circuit, a first wiring substrate, a second wiring substrate, first connection portions connecting the chip and a wiring layer on a first surface of the first wiring substrate and second connection portions connecting the second wiring substrate and a wiring layer on a second surface of the first wiring substrate, wherein one or more second connection portions arranged in a first row as viewed from the edge of the first substrate are provided at positions corresponding respectively to one or more of the first connection portions arranged in a first row as viewed from the edge and are arranged closer to the edge than the first connection portions arranged in the first row.

Inventors

Katsumi Kikuchi
Akira Miyata
Takanori Nishi
Kenji Nanba
Ayami YAMAGUCHI

Assignees

NEC CORPORATION

Dates

Publication Date: 20260512
Application Date: 20230317
Priority Date: 20220323

Claims (11)

1 . A quantum device, comprising: a chip including: a substrate; and a wiring layer made of superconducting material on the substrate; a first wiring substrate including: a first substrate; a first wiring layer on a first surface of the first substrate; a second wiring layer on a second surface of the first substrate opposite the first surface of the first substrate; and a plurality of through vias penetrating the first substrate between on the first wiring layer and the second wiring layer; and a second wiring substrate including: a second substrate; and a third wiring layer formed on a first surface of the second substrate; a plurality of first connection portions bonded between the wiring layer of the chip and the first wiring layer on the first surface of the first substrate arranged opposed to the chip; and a plurality of second connection portions bonded between the second wiring layer on the second surface of the first substrate and the third wiring layer on the first surface of the second substrate arranged opposed to the second surface of the first substrate, wherein, in the first wiring substrate, the plurality of second connection portions on the second surface of the first substrate include one or more second connection portions arranged in a first row as viewed from an edge of the first substrate and corresponding respectively to one or more first connection portions on the first surface of the first substrate arranged in a first row as viewed from the edge of the first substrate, the one or more second connection portions respectively positioned closer to the edge than the one or more first connection portions on the first surface of the first substrate arranged in the first row, wherein, in the first wiring substrate, the plurality of second connection portions on the second surface of the first substrate include at least one second connection portion on the second surface arranged in the first row as viewed from the edge of the first substrate, and the plurality of first connection portions on the first surface of the first substrate include: at least one first connection portion corresponding to the at least one second connection portion on the first surface arranged in the first row as viewed from the edge of the first substrate, the at least one second connection portion located closer to the edge than the at least one first connection portion, a distance between a second position of the at least one second connection portion on the second surface, and a first position of the at least one first connection portion on the first surface, the second position being a closest position of the second connection portion to the edge, the first position being a closest position of the first connection portion to the edge, with the second position on the second surface and the first position on the first surface projected on a same plane is set to a predetermined ratio or more of a distance between a center of the at least one first connection portion and the first position.
2 . The quantum device according to claim 1 , wherein, in the first wiring substrate, the plurality of second connection portions on the second surface of the first substrate includes at least one second connection portion on the second surface positioned first as viewed from an edge of at least one corner of four corners of the first substrate, is arranged closer to the edge of the at least one corner of the four corners than the corresponding first connection portion on the first surface positioned first as viewed from the edge of the at least one of the four corners.
3 . The quantum device according to claim 1 , wherein in the first wiring substrate, the plurality of second connection portions on the second surface of the first substrate include: at least one second connection portion on the second surface positioned first as viewed from an edge of a first corner of the first substrate; and at least another second connection portion on the second surface arranged in the first row as viewed from a side between neighboring two corners of the first substrate, the neighboring two corners including the first corner, wherein the plurality of first connection portions on the first surface of the first substrate include: at least one first connection portion on the first surface positioned first as viewed from an edge of the first corner of the first substrate; and at least another first connection portion on the first surface arranged in the first row as viewed from a side between the neighboring two corners, the at least one second connection portion and the at least another second connection portion on the second surface located respectively closer to the edge than the at least one first connection portion and the at least another first connection portion on the first surface.
4 . The quantum device according to claim 1 , wherein, in the first wiring substrate, the plurality of second connection portions on the second surface of the first substrate include plural second connection portions on the second surface arranged in the first row as viewed from each side of the first substrate respectively closer to the each side than corresponding plural first connection portions on the first surface arranged in the first row as viewed from the each side of the first substrate.
5 . The quantum device according to claim 1 , wherein, in the first wiring substrate, the second wiring layer on the second surface includes: a first connection terminal provided at an end of a first through via penetrating the first substrate; and/or a second connection terminal arranged at a position different from a position directly under a second through via penetrating the first substrate with a wiring routed from the second through via to the position, wherein the plurality of second connection portions on the second surface of the first substrate include a second connection portion having one end connected to a wiring pad of the third wiring layer of the second wiring substrate and having another end joined to the first connection terminal or the second connection terminals on the second face of the first substrate.
6 . The quantum device according to claim 1 , wherein the predetermined ratio is one-fifth or one-third.
7 . The quantum device according to claim 1 , wherein the plurality of first connection portions and the plurality of second connection portions each include a bump electrode.
8 . The quantum device according to claim 1 , wherein each of the plurality of first connection portions has a diameter smaller than a diameter of each of the plurality of second connection portions.
9 . The quantum device according to claim 1 , wherein the chip and the first wiring substrate include each a silicon substrate.
10 . The quantum device according to claim 1 , wherein the second wiring substrate is a multilayer substrate including a silicon substrate as a core material, and alternately laminated insulation layers and conductor layers formed on both sides of the core material, a lamination number being same on the both sides.
11 . The quantum device according to claim 1 , wherein the chip is flip-chip mounted on the first wiring substrate.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of the priority of Japanese patent application No. 2022-046286, filed on Mar. 23, 2022, the disclosure of which is incorporated herein in its entirety by reference thereto. FIELD This invention relates to a quantum device provided with a superconducting circuit. BACKGROUND A quantum chip provided with a superconducting circuit such as a superconducting quantum bit (qubit) and a coupler is formed on a substrate (e.g., silicon substrate) using a semiconductor micro-fabrication process. For pitch narrowing of connection terminals (electrodes) and wiring miniaturization of the quantum chip, the quantum chip is connected to a first wiring substrate (interposer) which performs pitch conversion and wiring routing. With an increase in the number of connection terminals due to an increase in the number of qubits included in the quantum chip, a connection terminal arranged on a surface facing the quantum chip is connected via a through via to a connection terminal arranged on an opposite side surface of the quantum chip, a signal is transmitted and received from the connection terminal provided on the opposite side surface. In the first wiring substrate (interposer), wiring is formed on a silicon substrate, which is similar to the substrate of a quantum chip. The quantum chip is flip-chip mounted on the first wiring substrate (interposer), with a circuit surface on which qubits are formed, faced down. In the first wiring substrate (interposer), such a configuration in which a dielectric other than a silicon is placed and a material other than a superconducting material is exposed on a first surface facing the circuit surface of the quantum chip is usually not adopted to prevent degradation of a qubit's transmission characteristic. Therefore, a wiring accommodation ratio of the first wiring substrate (interposer) cannot be increased. In order to increase a wiring accommodation ratio, for example, a configuration is used in which a plurality of wiring substrates are stacked. In this case, connection terminals on a surface of the first wiring substrate (interposer), opposite to a surface facing to a quantum chip, are directly connected to connection terminals on a first surface of a second wiring substrate (also called a package substrate), facing to the first wiring substrate, where connection to external circuit(s) is made from the connection terminals on a second surface of the second wiring substrate which is opposite to the first surface. As the second wiring substrate, a resin-based multilayer substrate may be used. In a three-dimensional mounting package composed of a plurality of wiring substrates, where the package includes a quantum chip and an interposer, as a substrate such as the interposer becomes thinner, warping or other deformation of the substrate impairs connection reliability. The warping of the substrate is also caused by a thermal stress due to a difference (mismatch) in coefficients of thermal expansion (coefficient of linear expansion) between materials subjected to thermal history. Underfill is used to increase a mounting strength (mechanical strength) of a wiring substrate on which a semiconductor chip is flip-chip mounted. An underfill material (e.g., epoxy resin, urethane resin, silicon resin, polyester resin, acrylic resin, etc.) is filled in a gap between the semiconductor chip and the first wiring substrate (interposer) and a gap between the first wiring substrate (interposer) and the second wiring substrate, for stress relaxation (Patent Literature (PTL) 1). However, it is known that circuit characteristics deteriorate in several to several tens of GHz (Gigahertz) band, for example, due to an effect of an underfill material which is an insulating adhesive material used to fix and seal the second wiring substrate and first wiring substrate (interposer). In addition, as described above, an underfill material is not used in the superconducting quantum circuit to avoid characteristic degradation (loss) due to a dielectric. Furthermore, in terms of thermal shrinkage, an underfill material is not used in consideration of occurrence of a warping and/or a stress strain thereof. [PTL 1] International Publication No. WO2020/122014 SUMMARY It is an object of the present disclosure to provide a quantum device enabled to suppress deformation or the like of a wiring substrate to improve connection reliability. According to the present disclosure, a quantum device includes: a chip including a substrate and a wiring layer made of superconducting material on the substrate;a first wiring substrate including a first substrate, a first wiring layer including a plurality of wirings formed on a first surface of the first substrate, a second wiring layer formed on a second surface opposite the first surface of the first substrate; and a plurality of through vias penetrating the first substrate and electrically connecti