US-12628575-B2 - Resistive switching memory device including dual active layer and array including the same

US12628575B2US 12628575 B2US12628575 B2US 12628575B2US-12628575-B2

Abstract

An embodiment of the present disclosure provides a resistive switching memory device including: a lower electrode; an amorphous metal oxide-based first active layer positioned on the lower electrode; an amorphous metal oxide-based second active layer positioned on the first active layer; and an upper electrode positioned on the second active layer, wherein the first active layer and the second active layer are made of the same substance but are different in electrical characteristic, thereby having a voluntary compliance current characteristic and a voluntary current rectification characteristic as a single device having a stable electrical characteristic, a method of manufacturing the resistive switching memory device, and an array including the resistive switching memory device.

Inventors

Hyung Koun Cho
Dong Su Kim
Hee Won Suh

Assignees

Research & Business Foundation Sungkyunkwan University

Dates

Publication Date: 20260512
Application Date: 20220929
Priority Date: 20210929

Claims (10)

1 . A resistive switching memory device comprising: a lower electrode; an amorphous metal oxide-based first active layer positioned on the lower electrode; an amorphous metal oxide-based second active layer positioned on the first active layer; and an upper electrode positioned on the second active layer, wherein the first active layer and the second active layer are made of the same substance but are different in electrical characteristic and wherein the resistive switching memory device has: (a) a first resistance state in which a first positive voltage is applied between the upper electrode and the lower electrode so the first active layer is set into a low-resistance state; (b) a second resistance state in which a second positive voltage is applied between the upper electrode and the lower electrode so the first active layer and the second active layer are set into a low-resistance state; and (c) a third resistance state in which a third positive voltage is applied between the upper electrode and the lower electrode so the first active layer and the second active layer are reset into a high-resistance state.
2 . The resistive switching memory device of claim 1 , wherein the amorphous metal oxide-based first active layer includes crystalline metal oxide nanoparticles.
3 . The resistive switching memory device of claim 1 , wherein the amorphous metal oxide-based second active layer includes crystalline metal oxide nanoparticles.
4 . The resistive switching memory device of claim 1 , wherein the first active layer and the second active layer are the same in reset driving voltage.
5 . The resistive switching memory device of claim 1 , wherein the first active layer or the second active layer has a voluntary rectification characteristic.
6 . The resistive switching memory device of claim 1 , wherein the first active layer and the second active layer include one or more selected from a group composed of CuO, Cu 2 O, Al 2 O 3 , Nb 2 O, NiO, MgO, TiO 2 , ZrO 2 , Nb:SrTiO 3 , Cr:SrTiO 3 , Cr:SrZrO 3 , ZnO, Co 3 O 4 , Fe 2 O 3 , Ag 2 O 3 , Bi 2 O 3 , Sb 2 O 3 , PbO 2 , RuO 2 , MnO 2 , Cr 2 O 3 , and a combination thereof.
7 . A resistive switching memory device array comprising: a first electrode extending in a first direction; a second electrode extending in a second direction crossing the first electrode; and an amorphous metal oxide-based first active layer and an amorphous metal oxide-based second active layer sequentially formed between the first electrode and the second electrode, wherein the first active layer and the second active layer are made of the same substance and are different in electrical characteristic and wherein the first active layer and the second active layer are different in set driving voltage.
8 . The resistive switching memory device array of claim 7 , wherein the amorphous metal oxide-based first active layer includes crystalline metal oxide nanoparticles.
9 . The resistive switching memory device array of claim 7 , wherein the amorphous metal oxide-based second active layer includes crystalline metal oxide nanoparticles.
10 . The resistive switching memory device array of claim 7 , wherein the first active layer and the second active layer include one or more selected from a group composed of CuO, Cu 2 O, Al 2 O 3 , Nb 2 O, NiO, MgO, TiO 2 , ZrO 2 , Nb:SrTiO 3 , Cr:SrTiO 3 , Cr:SrZrO 3 , ZnO, Co 3 O 4 , Fe 2 O 3 , Ag 2 O 3 , Bi 2 O 3 , Sb 2 O 3 , PbO 2 , RuO 2 , MnO 2 , Cr 2 O 3 , and a combination thereof.

Description

BACKGROUND OF THE INVENTION Field of the Invention The present disclosure relates to a resistive switching memory device and, more particularly, a resistive switching memory (RRAM) that can achieve a voluntary rectification characteristic, a voluntary limit current characteristic, and a multi-level implementation by including amorphous metal oxide-based dual active layers made of the same material. Description of the Related Art As high-density integration of volatile memories comes close to a limit, a nonvolatile memory rises as a next generation memory. A nonvolatile memory includes a phase change RAM (PRAM), a nano-floating gate memory (NFGM), a resistive RAM (ReRAM), a polymer RAM (PoRAM), a magnetic RAM (MRAM), molecule electronics, etc., and a RRAM (resistive RAM) of these devices is spotlighted as a next generation nonvolatile memory because of an easy manufacturing process, a high switching speed, and excellent durability in comparison to other devices. According to the technical development trend of the RRAM (Resistive RAM), a technology of achieving a cross point array using an RRAM is being developed as a strategy for further increasing integration of the RRAM. The cross point array using an RRAM in the early stage had some problems. First, there is influence (cross-talk) between adjacent cells when a cross point array using an RRAM is formed, thereby forming a sneak path and generating backflow of a current (sneak current), so there was a problem that data errors are generated. Further, there was a problem that it is required to suppress a current that is irreversibly generated when an RRAM is driven. In order to solve these problems, an external selection device and an external compliance current application device were applied to the existing cross point array using an RRAM, but it was impossible to use a simple metal-insulator-metal (MIM) structure, which is an advantage of the RRAM, and there was a limitation in integration. Second, a compliance current that controls conductivity is necessarily required to drive an RRAM. A current was limited in existing RRAMs using an external diode, a transistor, etc., but it was accompanied by a limitation in integration of the memory. Further, the added external diode, transistor, etc. could not follow the processing speed of an RRAM active layer, so there was a problem that the driving speed of the memory is limited. As another technical trend, a method of manufacturing an RRAM itself into a single device having functions not requiring help of an external diode, a transistor, etc. was proposed, and a structure including active layers made of different substances in dual layers was developed. However, it was difficult to uniformly control the number and size of polycrystalline grain boundaries, so electrical non-uniformity and instability of a device turned out as insuperable problems. Similarly, an RRAM using a phase change needs a heat transmit layer, so there was a difficulty in performing a complicated process. It was attempted to solve these problems by disclosing a resistance memory device including a lower electrode formed on a substrate, a variable resistive layer disposed on the lower electrode, and an upper electrode formed on the variable resistive layer, in which the variable resistive layer is composed of two or more oxide films, and a method of manufacturing the resistance memory device in Korean Patent No. 10-1401221 (titled, “Resistance memory device comprising crystalline oxidation film and method of fabricating the same”). However, since a crystalline oxidation film is included, it is difficult to control the number and size of grain boundaries and accordingly there is a limitation of electrical non-uniformity and instability of the device. Accordingly, there is a need for a technology that can achieve a multi-level implementation as a single device to keep the advantages of an RRAM and increase integration and that can solve the problem of a sneak current that is generated when forming an array and the problem that it is required to control a compliance current. CITATION LIST Patent Literature Patent Literature 1: Korean Patent No. 10-1401221 SUMMARY OF THE INVENTION An objective of the present disclosure for solving the problems described above is to provide a resistive switching memory device (RRAM) that can achieve a multi-level implementation as a single device. Another objective of the present disclosure is to provide a resistive switching memory device (RRAM) that solves the problem of a sneak current that is generated between adjacent cells when a cross point array is formed, and solves the problem that it is required to control a compliance current, as a single device. Another objective of the present disclosure is to provide a resistive switching memory device that solves the problem of controlling grain boundaries that is generated when an active layer is formed into a crystalline dual layer, and solves the corresponding prob