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US-12628578-B2 - Substrate processing method

US12628578B2US 12628578 B2US12628578 B2US 12628578B2US-12628578-B2

Abstract

Provided is a method of processing a substrate in a reaction chamber, more particularly to a method of increasing a wet etch rate of SiCN layer in order to reduce an overhang from a SiCN layer formed on a stepped structure. The method comprises supplying a carbon-containing silicon source and a nitrogen gas simultaneously while applying a power, followed by performing a post treatment, wherein the wet etch rate of SiCN layer is modulated by the amount of nitrogen source supplied.

Inventors

  • Jeonghoon Jang
  • KiKang Kim
  • Youngmin Kim
  • Haein Kim
  • JeungHoon Han

Assignees

  • ASM IP HOLDING B.V.

Dates

Publication Date
20260512
Application Date
20241112

Claims (19)

  1. 1 . A method of processing a substrate in a reaction chamber, comprising: providing the substrate into the reaction chamber; forming a stack layer comprising an insulation layer and a first sacrificial layer on the substrate; forming a stepped structure on the stack layer, wherein the stepped structure comprises an upper surface, a lower surface and a side surface connecting the upper surface and the lower surface; forming a second sacrificial layer on the stepped structure; forming a third sacrificial layer on the second sacrificial layer; and performing a wet etching to remove the second sacrificial layer and the third sacrificial layer from the side surface, so that the second sacrificial layer and the third sacrificial layer remain on the upper surface and the lower surface, wherein a wet etch rate of the third sacrificial layer is modulated by supplying a nitrogen source during forming the third sacrificial layer, and wherein the insulation layer is a SiO 2 layer and the first sacrificial layer is a SiN layer, and wherein the third sacrificial layer is a SiCN layer formed by repeating a cycle comprising: supplying a second silicon source and the nitrogen source to the substrate simultaneously to form the SiCN layer while applying a second power to the reaction chamber, wherein the second silicon source comprises a carbon constituent, and a wet etch rate of the SiCN layer is modulated by reducing a carbon constituent by supplying the nitrogen source, and performing a post treatment by applying a third power to the reaction chamber, wherein the nitrogen source is further supplied during the post treatment.
  2. 2 . The method of claim 1 , wherein the second sacrificial layer is a SiN layer formed by repeating a cycle comprising: supplying a first silicon source to the substrate; supplying the nitrogen source as a reactant to the substrate; and applying a first power to the reaction chamber to activate the nitrogen source, wherein the first silicon source comprises carbon-free constituents.
  3. 3 . The method of claim 2 , wherein the first silicon source comprises at least one of TSA, (SiH 3 ) 3 N; DSO, (SiH 3 ) 2 ; SiCl 4 ; HCD, Si 2 Cl 6 ; Si 3 H 8 ; DCS, SiH 2 Cl 2 ; SiHI 3 ; SiH 2 I 2 ; or a mixture thereof.
  4. 4 . The method of claim 2 , wherein the nitrogen source comprises at least one of N 2 , NH 3 , NH 4 , N 2 H 2 , N 2 H 4 , or a mixture thereof.
  5. 5 . The method of claim 2 , wherein the first power is a high frequency power at between about 30 W and about 1,200 W.
  6. 6 . The method of claim 1 , wherein the nitrogen source is supplied at between about 100 sccm and about 20,000 sccm during forming the SiCN layer.
  7. 7 . The method of claim 1 , wherein an overhang is reduced from the stepped structure.
  8. 8 . The method of claim 1 , wherein the second silicon source comprises at least one of aminosilane, alkoxysilane, alkylsilane, or a mixture thereof.
  9. 9 . The method of claim 8 , wherein the second silicon source comprises at least one of DSMA, (SiH 3 ) 2 NMe; DSEA, (SiH 3 ) 2 NEt; DSIPA, (SiH 3 ) 2 N (iPr); DSTBA, (SiH 3 ) 2 N (tBu); DEAS, SiH 3 NEt 2 ; DTBAS, SiH 3 N(tBu) 2 ; BDEAS, SiH 2 (NEt 2 ) 2 ; BDMAS, SiH 2 (NMe 2 ) 2 ; BTBAS, SiH 2 (NHtBu) 2 ; BITS, SiH 2 (NHSiMe 3 ) 2 ; DIPAS, SiH 3 N(iPr) 2 ; TEOS, Si(OEt) 4 ; 3DMAS, SiH(N(Me) 2 ) 3 ; BEMAS, SiH 2 [N(Et)(Me)] 2 ; AHEAD, Si 2 (NHEt) 6 ; TEAS, Si(NHEt) 4 ; 4 MS, Si(CH 3 ) 4 , or a mixture thereof.
  10. 10 . The method of claim 1 , wherein the nitrogen source comprises at least one of N 2 , NH 3 , NH 4 , N 2 H 2 , N 2 H 4 , or a mixture thereof.
  11. 11 . The method of claim 1 , wherein the second power is between about 30 W and about 1,200 W.
  12. 12 . The method of claim 1 , wherein the third power is between about 30 W and about 1,200 W.
  13. 13 . The method of claim 1 , wherein the second power and the third power comprise a high frequency power and a low frequency power.
  14. 14 . The method of claim 1 , wherein the wet etch rate ratio of the third sacrificial layer to the second sacrificial layer is between about 1:2 and about 1:300.
  15. 15 . The method of claim 14 , wherein the wet etch rate ratio of the third sacrificial layer to the second sacrificial layer is between about 1:10 and about 1:100.
  16. 16 . The method of claim 1 , wherein a wet etch rate of the second sacrificial layer is between about 0.2 Å/second and about 20 Å/second.
  17. 17 . The method of claim 1 , wherein a wet etch rate of the third sacrificial layer is between about 0.01 Å/second and about 0.3 Å/second.
  18. 18 . The method of claim 1 , further comprising supplying an inert gas continuously to purge the reaction chamber while forming the second sacrificial layer and the third sacrificial layer.
  19. 19 . The method of claim 1 , further comprising: forming an interlayer insulation layer on the stepped structure; forming a via contact through the interlayer insulation layer to the third sacrificial layer; etching the first sacrificial layer, the second sacrificial layer and the third sacrificial layer; and filling a space formed by the etching and the via contact with a conductive layer, wherein the conductive layer comprises at least one of polysilicon, aluminum, copper and tungsten, or a mixture thereof.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application Ser. No. 63/599,004 filed Nov. 15, 2023 titled SUBSTRATE PROCESSING METHOD, the disclosure of which is hereby incorporated by reference in its entirety. FIELD OF INVENTION The disclosure relates to a method of processing a substrate in a reaction chamber, more particularly to a method of removing an overhang from a film layer formed on a stepped structure. BACKGROUND OF THE DISCLOSURE As the line width of a semiconductor device circuit continues to shrink, a 3D (three dimensional) structure was introduced to a non-volatile semiconductor device for high degree of integration. For instance, by vertically stacking up multiple gate structures, a highly integrated NAND semiconductor device is enabled in a limited space on a substrate. A gate electrode of each gate of 3D NAND semiconductor device is connected to a word line via a via contact hole. To that end, 3D gate electrode is shaped in a form of staircase and each of the gate electrode is connected to the word line through the end of each stair and the via contact hole. FIG. 1A to FIG. 1I illustrate a conventional method of forming a gate structure of 3D NAND semiconductor device on a stepped structure 10. In FIG. 1A, a stack layer comprising an insulation layer 100 (100a, 100b, 100c and 100d) and a first sacrificial layer 110 (110a, 110b, 110c and 110d) may be formed and stacked alternately. The insulation layer 100 and the first sacrificial layer 110 may be formed by CVD (Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition). The insulation layer may comprise SiO2 and the first sacrificial layer may comprise SiN. In FIG. 1B, a stepped structure 10 may be formed. The stepped structure 10 may be formed via, for instance, reactive ion etching and resist slimming to the stack layer. The stepped structure 10 may comprise an upper surface 120, a side surface 140, and a lower surface 160 connecting the upper surface 120 and the lower surface 160. In FIG. 1C, a second sacrificial layer 200 may be formed uniformly on the stepped structure 10. The second sacrificial layer 200 may comprise SiN. The second sacrificial layer 200 may be formed using an in-situ plasma by applying a power to a reaction chamber. For instance, the second sacrificial layer may be formed by PEALD (Plasma Enhanced Atomic Layer Deposition). The second sacrificial layer 200 may be a contact pad for via contacts 230 (230a, 230b, 230c and 230d) as shown in FIG. 1G. In FIG. 1D, a third sacrificial layer 210 may be formed uniformly on the second sacrificial layer 200. The third sacrificial layer 210 may comprise SiCN. The third sacrificial layer 210 may be formed using an in-situ plasma by applying a power to the reaction chamber. For instance, the third sacrificial layer 210 may be formed by PEALD (Plasma Enhanced Atomic Layer Deposition). The third sacrificial layer 210 may be a mask layer to prevent the via contact from penetrating the contact pad (i.e. a second sacrificial layer 200) into the first sacrificial layer and another first sacrificial layer in the subsequent process as shown in FIG. 2 (e.g. 110b and 110c in FIG. 2). Therefore, the third sacrificial layer 210 may be harder than the second sacrificial layer 200. For instance, the third sacrificial layer 210 may have a wet etch rate lower than that of the second sacrificial layer 200. It is known that a SiCN layer is harder than a SiN layer. Therefore, a wet etch selectivity between the SiCN layer (i.e. a third sacrificial layer) and the SiN layer (i.e. a second sacrificial layer) may be maintained. In FIG. 1E, an isotropic etch may be performed. For instance, a wet etch may be performed. As described above, an in-situ plasma may be applied to form the second sacrificial layer 200 and the third sacrificial layer 210. Due to a directionality of the plasma species such as ions, a layer located perpendicular to the moving direction of ions may be densified and hardened by ion-bombardment. That is, a layer formed on the upper surface and a layer formed on the lower surface of the stepped structure may be densified and hardened. On the contrary, a layer which is located laterally to the moving direction of ions may be less densified and less hardened. That is, a layer formed on the side surface of the stepped structure may be less densified and less hardened than a layer formed on the upper surface and the lower surface. Therefore, a layer formed on the upper surface and the lower surface may remain and a layer formed on the side surface may be removed due to a wet etch selectivity during the wet etch as shown in FIG. 1E. The third sacrificial layer 210 is a mask layer to protect the second sacrificial layer 200 from being penetrated by via contacts 230 (230a, 230b, 230c and 230d) as shown in FIG. 2. In other words, the third sacrificial layer 210 may be denser and harder than the second sacrificial layer 2