US-12628596-B2 - Method of manufacturing integrated circuit device

Abstract

A method of manufacturing an integrated circuit device includes preparing a semiconductor substrate having an active area and a field area, sequentially forming a lower insulation layer, a buried layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the semiconductor substrate, removing a portion of the third sacrificial layer to form a first sacrificial pattern, removing a portion of the second sacrificial layer and the first sacrificial pattern to form a second sacrificial pattern, removing a portion of the first sacrificial layer and the second sacrificial pattern to form a third sacrificial pattern, removing a portion of the buried layer and the third sacrificial pattern to form a buried pattern, and removing a portion of the lower insulation layer and a portion of the semiconductor substrate by using the buried pattern as an etch mask to form a word line trench.

Inventors

• Youngwoo Kim
• Yonghan PARK
• Jiho Park
• Geumjung Seong
• Seunguk Han

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20230720

Priority Date

20220831

Claims (20)

1. 1 . A method of manufacturing an integrated circuit device, the method comprising: preparing a semiconductor substrate having an active area and a field area; sequentially forming a lower insulation layer, a buried layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the semiconductor substrate; removing a portion of the third sacrificial layer to form a first sacrificial pattern; removing a portion of the second sacrificial layer and the first sacrificial pattern to form a second sacrificial pattern; removing a portion of the first sacrificial layer and the second sacrificial pattern to form a third sacrificial pattern; removing a portion of the buried layer and the third sacrificial pattern to form a buried pattern; and removing a portion of the lower insulation layer and a portion of the semiconductor substrate by using the buried pattern as an etch mask to form a word line trench, wherein the first sacrificial layer comprises polysilicon.
2. 2 . The method of claim 1 , wherein the forming of the second sacrificial pattern comprises: forming a first mask layer conformally covering the first sacrificial pattern; partially removing the first mask layer to form a first mask pattern and to expose the first sacrificial pattern and the second sacrificial layer; and removing a portion of the second sacrificial layer and the first sacrificial pattern by using the first mask pattern as an etch mask.
3. 3 . The method of claim 1 , wherein the forming of the third sacrificial pattern comprises: forming a second mask layer conformally covering the second sacrificial pattern; partially removing the second mask layer to form a second mask pattern and to expose the second sacrificial pattern and the first sacrificial layer; and removing a portion of the first sacrificial layer and the second sacrificial pattern by using the second mask pattern as an etch mask.
4. 4 . The method of claim 3 , wherein the removing of the portion of the first sacrificial layer comprises: at least partially removing the second mask pattern through an etching process; and cleaning the semiconductor substrate by using hydrogen fluoride (HF).
5. 5 . The method of claim 1 , wherein the forming of the buried pattern comprises: forming a third mask layer conformally covering the third sacrificial pattern; partially removing the third mask layer to form a third mask pattern and to expose the third sacrificial pattern; and removing a portion of the buried layer and the third sacrificial pattern by using the third mask pattern as an etch mask.
6. 6 . The method of claim 1 , wherein the forming of the word line trench comprises: partially removing each of the lower insulation layer and the semiconductor substrate by using the buried pattern as an etch mask; and ashing the semiconductor substrate in an oxygen-containing atmosphere.
7. 7 . The method of claim 1 , wherein each of the second sacrificial layer and the third sacrificial layer comprises a double layer with a first layer of the double layer having an etch selectivity with respect to a second layer of the double layer.
8. 8 . The method of claim 7 , wherein the double layer of at least one of the second sacrificial layer and the third sacrificial layer comprises a spin-on hardmask film as the first layer and silicon oxynitride as the second layer, the silicon oxynitride covering the spin-on hardmask film.
9. 9 . The method of claim 1 , wherein the buried layer comprises a single layer including an amorphous carbon layer.
10. 10 . The method of claim 1 , wherein the word line trench passes through the active area and the field area.
11. 11 . A method of manufacturing an integrated circuit device, the method comprising: forming a semiconductor substrate having a peripheral circuit area and a cell array area; forming a lower insulation layer on the semiconductor substrate; forming a buried layer on the lower insulation layer; forming a first sacrificial layer on the buried layer, the first sacrificial layer including polysilicon; forming a second sacrificial layer, including a first lower sacrificial layer and a first upper sacrificial layer having an etch selectivity with respect to each other, on the first sacrificial layer; forming a third sacrificial layer, including a second lower sacrificial layer and a second upper sacrificial layer having an etch selectivity with respect to each other, on the second sacrificial layer; removing a portion of the third sacrificial layer to form a first sacrificial pattern; removing a portion of the second sacrificial layer and the first sacrificial pattern to form a second sacrificial pattern; removing a portion of the first sacrificial layer and the second sacrificial pattern to form a third sacrificial pattern; removing a portion of the buried layer and the third sacrificial pattern to form a buried pattern; and removing a portion of the lower insulation layer and a portion of the semiconductor substrate by using the buried pattern as an etch mask to form a word line trench.
12. 12 . The method of claim 11 , wherein the forming of the buried pattern comprises: forming a mask layer conformally covering the third sacrificial pattern; partially removing the mask layer to form a mask pattern and expose the third sacrificial pattern; forming a word line mask exposing the cell array area; and removing a portion of the buried layer and the third sacrificial pattern by using the mask pattern as an etch mask to form the buried pattern.
13. 13 . The method of claim 11 , wherein the forming of the buried pattern comprises: forming a mask layer conformally covering the third sacrificial pattern; forming a word line mask exposing the cell array area; partially removing the mask layer to form a mask pattern and expose the third sacrificial pattern; and removing a portion of the buried layer and the third sacrificial pattern by using the mask pattern as an etch mask to form the buried pattern.
14. 14 . The method of claim 11 , wherein the forming of the word line trench comprises, after the word line trench is formed in the semiconductor substrate by using the buried pattern as an etch mask, removing the buried pattern in an oxygen-containing atmosphere.
15. 15 . The method of claim 11 , wherein each of the first lower sacrificial layer and the second lower sacrificial layer comprises a spin-on hardmask, and each of the first upper sacrificial layer and the second upper sacrificial layer comprises silicon oxynitride.
16. 16 . The method of claim 11 , wherein the buried layer comprises a single layer including an amorphous carbon layer.
17. 17 . A method of manufacturing an integrated circuit device, the method comprising: forming a semiconductor substrate having a peripheral circuit area and a cell array area including an active area and a field area; forming a lower insulation layer on the semiconductor substrate; forming a buried layer on the lower insulation layer; forming a first sacrificial layer on the buried layer, the first sacrificial layer including polysilicon; forming a second sacrificial layer, including a first lower sacrificial layer and a first upper sacrificial layer having an etch selectivity with respect to each other, on the first sacrificial layer; forming a third sacrificial layer, including a second lower sacrificial layer and a second upper sacrificial layer having an etch selectivity with respect to each other, on the second sacrificial layer; removing the third sacrificial layer to form a first sacrificial pattern exposing the second sacrificial layer; forming a first mask layer conformally covering the first sacrificial pattern and the exposed second sacrificial layer; partially removing the first mask layer to form a first mask pattern covering a sidewall of the first sacrificial pattern; removing a portion of the second sacrificial layer and the first sacrificial pattern by using the first mask pattern as an etch mask to form a second sacrificial pattern exposing the first sacrificial layer; forming a second mask layer conformally covering the second sacrificial pattern and the exposed first sacrificial layer; partially removing the second mask layer to form a second mask pattern covering a sidewall of the second sacrificial pattern; removing a portion of the first sacrificial layer and the second sacrificial pattern by using the second mask pattern as an etch mask to form a third sacrificial pattern exposing the buried layer; forming a third mask layer conformally covering the third sacrificial pattern and the exposed buried layer; partially removing the third mask layer to form a third mask pattern covering the buried layer and a sidewall of the third sacrificial pattern; removing a portion of the buried layer and the third sacrificial pattern by using the third mask pattern as an etch mask to form a buried pattern; and removing a portion of the lower insulation layer and a portion of the semiconductor substrate by using the buried pattern as an etch mask to form a word line trench passing through the active area and the field area.
18. 18 . The method of claim 17 , wherein the forming of the third sacrificial pattern comprises removing the second mask pattern by using hydrogen fluoride (HF).
19. 19 . The method of claim 17 , wherein the forming of the buried pattern comprises forming a word line mask covering the peripheral circuit area.
20. 20 . The method of claim 17 , wherein the first sacrificial layer comprises a single layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0110155, filed on Aug. 31, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND Example embodiments relate to a method of manufacturing an integrated circuit device, and more particularly, to a method of manufacturing an integrated circuit device including a buried channel array transistor. Recently, as the degree of integration of integrated circuit devices increases progressively, a structure of integrated circuit devices including a buried channel array transistor (BCAT) and having a type or structure where a plurality of word lines are buried in a substrate has been proposed. Therefore, various researches for improving and stabilizing the operation and reliability of BCATs are being done. SUMMARY Example embodiments provide a method of manufacturing an integrated circuit device, in which the degree of integration of the integrated circuit device increases, and thus, electrical reliability is maintained despite a reduction in area of a device region. According to some example embodiments, there is provided a method of manufacturing an integrated circuit device, the method including preparing a semiconductor substrate having an active area and a field area, sequentially forming a lower insulation layer, a buried layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the semiconductor substrate, removing a portion of the third sacrificial layer to form a first sacrificial pattern, removing a portion of the second sacrificial layer and the first sacrificial pattern to form a second sacrificial pattern, removing a portion of the first sacrificial layer and the second sacrificial pattern to form a third sacrificial pattern, removing a portion of the buried layer and the third sacrificial pattern to form a buried pattern, and removing a portion of the lower insulation layer and a portion of the semiconductor substrate by using the buried pattern as an etch mask to form a word line trench, wherein the first sacrificial layer includes polysilicon. According to various example embodiments, there is provided a method of manufacturing an integrated circuit device, the method including forming a semiconductor substrate having a peripheral circuit area and a cell array area, forming a lower insulation layer on the semiconductor substrate, forming a buried layer on the lower insulation layer, forming a first sacrificial layer on the buried layer, the first sacrificial layer including polysilicon, forming a second sacrificial layer, including a first lower sacrificial layer and a first upper sacrificial layer having an etch selectivity with respect to each other, on the first sacrificial layer, forming, on the second sacrificial layer, a third sacrificial layer, including a second lower sacrificial layer and a second upper sacrificial layer having an etch selectivity with respect to each other, removing a portion of the third sacrificial layer to form a first sacrificial pattern, removing a portion of the second sacrificial layer and the first sacrificial pattern to form a second sacrificial pattern, removing a portion of the first sacrificial layer and the second sacrificial pattern to form a third sacrificial pattern, removing a portion of the buried layer and the third sacrificial pattern to form a buried pattern, and removing a portion of the lower insulation layer and a portion of the semiconductor substrate by using the buried pattern as an etch mask to form a word line trench. According to various example embodiments, there is provided a method of manufacturing an integrated circuit device, the method including forming a semiconductor substrate having a peripheral circuit area and a cell array area that includes an active area and a field area, forming a lower insulation layer on the semiconductor substrate, forming a buried layer on the lower insulation layer, forming a first sacrificial layer on the buried layer, the first sacrificial layer including polysilicon, forming a second sacrificial layer, including a first lower sacrificial layer and a first upper sacrificial layer having an etch selectivity with respect to each other, on the first sacrificial layer, forming, on the second sacrificial layer, a third sacrificial layer, including a second lower sacrificial layer and a second upper sacrificial layer having an etch selectivity with respect to each other, removing the third sacrificial layer to form a first sacrificial pattern exposing the second sacrificial layer, forming a first mask layer conformally covering the first sacrificial pattern and the exposed second sacrificial layer, partially removing the first mask layer to form a first mask pattern covering a sidewall of the first sacrificial pattern, removing a portion of the secon