US-12628597-B2 - Frame mask for singulating wafers by plasma etching

US12628597B2US 12628597 B2US12628597 B2US 12628597B2US-12628597-B2

Abstract

The present disclosure relates to plasma dicing of wafer. More specifically, the present disclosure is directed to frame masks and methods for plasma dicing wafers utilizing frame masks. The frame mask includes a mask frame, wherein the mask frame includes a top ring mask support and a side ring mask support. A plurality of mask segments suspended from the top ring mask support by segment supports, the mask segments are configured to define dicing channels on a blank wafer. The frame mask is configured to removably sit onto a frame lift assembly in a plasma chamber of a plasma dicing tool, when fitted onto the frame lift assembly, the mask segments are disposed above a wafer on a wafer ring frame for plasma dicing. The mask frame is configured to enable flow of plasma therethrough to the wafer to etch the wafer to form dicing channels defined by the mask segments.

Inventors

Dzafir Bin Mohd SHARIFF
Il Kwon Shim
Enrique E. Sarile, JR.
Jackson Fernandez ROSARIO
Ronnie M. DE VILLA
Chan Loong Neo

Assignees

UTAC Headquarters Pte. Ltd.

Dates

Publication Date: 20260512
Application Date: 20221111

Claims (19)

1 . A frame mask for plasma dicing wafers comprising: a mask frame, wherein the mask frame includes a top ring mask support, a side ring mask support; a plurality of mask segments which are suspended from the top ring mask support by segment supports, the segment supports connect the mask segments to the top ring mask support, wherein spaces between the mask segments define dicing channels on a blank wafer; and wherein the frame mask is configured to removably sit onto a frame lift assembly in a plasma chamber of a plasma dicing tool, when fitted onto the frame lift assembly, the mask segments are disposed above a wafer on a wafer ring frame for plasma dicing, the mask frame is configured to enable flow of plasma therethrough to the wafer to dice the wafer along dicing channels defined by the spaces between the mask segments, and the mask frame, including the mask segments, is not eroded by the flow of plasma used in dicing the wafer.
2 . The frame mask of claim 1 , wherein the top ring mask support includes top ring mask support members from which the mask segments are suspended.
3 . The frame mask of claim 1 , wherein the mask segments include a top and a bottom major mask segment surfaces with side mask segment surfaces, the top major mask segment surface is smaller than the bottom major mask segment surface, the side mask segment surfaces have an outwardly sloped profile.
4 . The frame mask of claim 3 , wherein the mask segments include elongated mask segment members in a first direction, and gaps between adjacent mask segments define dicing channels in the first direction.
5 . The frame mask of claim 3 , wherein the mask segments include grid-patterned mask segment members in first and second directions, and spaces between adjacent mask segments define the dicing channels on the wafer in the first and second directions for dicing the wafer.
6 . The frame mask of claim 1 , wherein the side ring mask support has an inwardly sloped profile configured to be fitted onto the frame lift assembly.
7 . The frame mask of claim 6 , wherein the frame lift assembly includes a frame lift ring on a top of the frame lift assembly, the frame lift ring has an outwardly sloped inner side surface which is complementary with the inwardly sloped profile of the side ring mask support.
8 . The frame mask of claim 6 , wherein the mask frame further comprises a bottom ring mask support surrounding the mask segments, the bottom ring mask support is smaller than the top ring mask support, the side ring mask support extends from the top ring mask support to the bottom ring mask support.
9 . The frame mask of claim 3 , the frame mask further comprises a cap layer disposed on the bottom major mask segment surface of the mask segments.
10 . The frame mask of claim 9 , wherein the cap layer is a heat resistant layer.
11 . The frame mask of claim 10 , wherein the cap layer is a high temperature silicone rubber material layer.
12 . The frame mask of claim 1 , wherein the frame mask is formed of the same material as the frame lift assembly to avoid thermal mismatch.
13 . The frame mask of claim 12 , wherein the frame mask and the frame lift assembly are formed of Aluminium (Al).
14 . A frame mask for plasma dicing wafers comprising: a mask frame, wherein the mask frame includes a top ring mask support, a side ring mask support, a bottom ring mask support; a plurality of mask segments suspended from the top ring mask support by segment supports, the segment supports connect the mask segments to the top ring mask support, the mask segments are disposed along first and second orthogonal directions to form a grid pattern, wherein spaces between the mask segments define dicing channels on a blank wafer in the first and second orthogonal directions, wherein the mask segments include a top and a bottom major mask segment surfaces with side mask segment surfaces, the top major mask segment surface is smaller than the bottom major mask segment surface, the side mask segment surfaces have an outwardly sloped profile; a cap layer disposed on the bottom major mask segment surface of the mask segments; and wherein the frame mask is configured to removably sit onto a frame lift assembly in a plasma chamber of a plasma dicing tool, when fitted onto the frame lift assembly, the mask segments are disposed above a wafer on a wafer ring frame for plasma dicing, and the mask frame is configured to enable flow of plasma therethrough to the wafer to dice the wafer along dicing channels defined by the spaces between the mask segments, and the mask frame, including the mask segments, is not eroded by the flow of plasma used in dicing the wafer.
15 . The frame mask of claim 14 , wherein the side ring mask support has an inwardly sloped profile configured to be fitted onto the frame lift assembly.
16 . The frame mask of claim 15 , wherein the frame lift assembly includes a frame lift ring on a top of the frame lift assembly, the frame lift ring has an outwardly sloped inner side surface which is complementary with the inwardly sloped profile of the side ring mask support.
17 . The frame mask of claim 15 , wherein the mask frame further comprises the bottom ring mask support surrounding the mask segments, the bottom ring mask support is smaller than the top ring mask support, the side ring mask support extends from the top ring mask support to the bottom ring mask support.
18 . The frame mask of claim 14 , wherein the cap layer is a heat resistant layer.
19 . The frame mask of claim 14 , wherein the frame mask is formed of the same material as the frame lift assembly to avoid thermal mismatch.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the benefit of U.S. Provisional Application Ser. No. 63/278,489, filed on Nov. 12, 2021, which is incorporated by reference in its entirety for all purposes. FIELD OF THE INVENTION The present disclosure generally relates to plasma dicing of semiconductor wafers. More specifically, the present disclosure is directed to frame masks and methods for utilizing the frame masks for plasma dicing. BACKGROUND In semiconductor processing, a wafer is processed to form a plurality of devices thereon. After the devices are formed, the wafer is diced to separate the devices into individual dies. Conventional techniques for dicing employ the use of a dicing saw. The saw cuts the wafer along the x-direction and the y-direction saw lines, one at a time, to separate the wafer into individual dies. Sawing, however, takes time, which slows down the processing throughput. In addition, mechanical sawing causes vibration when cutting the wafer. The vibration may cause cracks in the dies, such as the back-end dielectric, which may impact yields negatively. To combat the issues of sawing, plasma dicing has been investigated. Plasma dicing entails mounting a wafer onto a wafer ring and inserting the wafer ring with the wafer into a plasma chamber for etching. Unlike mechanical sawing, the plasma etch process singulates the wafer into individual dies in a single plasma etch step without any vibration issues. This significantly improves throughput as well as avoids reliability issues due to cracking. In addition, plasma dicing avoids vibration which may cause cracking in the dies. However, plasma dicing requires pre and post-plasma dicing processes. The pre-plasma dicing process includes a coating process that forms a hard mask layer, such as a silicon oxide layer on the wafer, and a patterning process to form the hard mask. The patterning process includes laser etching. Laser etching requires individual laser cuts in the x-direction and the y-direction to form the etch mask used for plasma dicing. Laser etching tools are quite expensive and laser etching is time-consuming due to the required individual cuts. As for the post-plasma dicing process, it includes removing the mask, further incurring additional processing time. Based on the foregoing discussion, there is a desire to provide fast and economical plasma dicing processes. SUMMARY Frame masks, including systems and methods thereof, are disclosed. In one embodiment, a frame mask for plasma dicing wafers includes a mask frame, wherein the mask frame includes a top ring mask support and a side ring mask support. A plurality of mask segments suspended from the top ring mask support by segment supports, the mask segments are configured to define dicing channels on a blank wafer. The frame mask is configured to removably sit onto a frame lift assembly in a plasma chamber of a plasma dicing tool, when fitted onto the frame lift assembly, the mask segments are disposed above a wafer on a wafer ring frame for plasma dicing. The mask frame is configured to enable flow of plasma therethrough to the wafer to etch the wafer to form dicing channels defined by the mask segments. In another embodiment, a method for plasma dicing a wafer utilizing a frame mask includes providing a frame mask in a plasma chamber, the frame mask includes a mask frame for supporting a plurality of mask segments configured to define dicing channels of a wafer. A wafer frame ring assembly with a wafer for plasma dicing on wafer ring assembly holder of a frame lift assembly is disposed in a plasma chamber of a plasma dicing tool. The frame mask is placed onto a frame lift ring on a top of the frame lift assembly, wherein the mask segments are disposed over the wafer. The frame lift assembly is lowered so that the wafer on the wafer ring frame assembly is fixed to an electrostatic chuck in the plasma chamber. The method also includes performing plasma dicing of the wafer in the plasma chamber. In yet another embodiment, a method for plasma dicing wafers utilizing frame masks includes providing a first frame mask in a first plasma chamber and a second frame mask in a second plasma chamber, the first and second frame masks include a mask frame for supporting a plurality of mask segments configured to define dicing channels of a wafer, the first frame mask is configured to provide plasma dicing channels in a first direction, and the second frame mask is configured to provide plasma dicing channels in a second direction. A wafer frame ring assembly with a wafer for plasma dicing is mounted on wafer ring assembly holder of a frame lift assembly disposed in the first plasma chamber of a plasma dicing tool. The first frame mask is placed onto a frame lift ring on a top of the frame lift assembly, wherein the mask segments are disposed over the wafer. The frame lift assembly is lowed so that the wafer on the wafer ring frame assembly is fixed to an electrostatic