US-12628604-B2 - Processing methods and cluster tools for forming semiconductor devices

US12628604B2US 12628604 B2US12628604 B2US 12628604B2US-12628604-B2

Abstract

Semiconductor devices (e.g., GAA device structures) and processing methods and cluster tools for forming GAA device structures are described. The cluster tools for forming GAA device structures comprise a first etch chamber, a second etch chamber, and a third etch chamber. Each of the first etch chamber and the second etch chamber independently comprises a single-wafer chamber or an immersion chamber. One or more of the first etch chamber or the second etch chamber may be a wet etch chamber. In some embodiments, at least one of the first etch chamber, the second etch chamber, and the third etch chamber is a dry etch chamber. The cluster tool described herein advantageously reduces the number of cleaning processes, the total time between cleaning and processing operations, variations in time between processing and variation in sidewall loss compared to conventional cluster tools.

Inventors

Benjamin COLOMBEAU
Balasubramanian Pranatharthiharan
Lequn Liu
Brian K. Kirkpatrick

Assignees

APPLIED MATERIALS, INC.

Dates

Publication Date: 20260512
Application Date: 20230725

Claims (8)

1 . A processing method for forming a gate-all-around (GAA) device, comprising: removing a dummy gate polysilicon layer from a dummy gate oxide layer in a first etch chamber, wherein the dummy gate oxide layer is disposed on a fin on the substrate, wherein the fin comprises alternating layers of a first material and a second material, wherein the first material is different than the second material; removing the dummy gate oxide layer in a second etch chamber; and removing the layers of the second material in a third etch chamber to expose a spacer material, wherein the first etch chamber, the second etch chamber, and the third etch chamber are in a cluster tool, wherein there is an absence of a cleaning step between removing the dummy gate polysilicon layer and removing the dummy gate oxide layer, and between removing the dummy gate oxide layer and removing the layers of the second material, and wherein an absolute value of the spacer material loss and a variation in spacer material loss is reduced compared to a processing method including a cleaning step.
2 . The processing method of claim 1 , wherein the first material comprises silicon or silicon germanium and wherein the second material comprise silicon or silicon germanium.
3 . The processing method of claim 1 , wherein each of the first etch chamber and second etch chamber independently comprises a single-wafer chamber or an immersion chamber.
4 . The processing method of claim 3 , wherein one or more of the first etch chamber or the second etch chamber is a wet etch chamber.
5 . The processing method of claim 4 , wherein one or more of the first etch chamber or the second etch chamber comprises a plurality of stacked single-wafer wet etch chambers.
6 . The processing method of claim 1 , wherein at least one of the first etch chamber, the second etch chamber, and the third etch chamber is a dry etch chamber.
7 . The processing method of claim 1 , further comprising one or more of: forming a thin oxide layer on each of the layers of the first material in a fourth processing chamber; forming a high-K metal oxide layer on the thin oxide layer in a fifth processing chamber; or forming a metal nitride layer on the high-K metal oxide layer in a sixth processing chamber.
8 . The processing method of claim 7 , wherein the thin oxide layer is deposited directly on the first material, formed directly on the first material by exposing the first material to ozone (O 3 ) and water (H 2 O), or formed directly on the first material from a dielectric material.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Application No. 63/400,221, filed Aug. 23, 2022, and U.S. Provisional Application No. 63/392,258, filed Jul. 26, 2022, the entire disclosures of which are hereby incorporated by reference herein. TECHNICAL FIELD Embodiments of the present disclosure generally relate to semiconductor devices and, more particularly, to gate-all-around (GAA) device structures and processing methods and cluster tools for forming GAA device structures. BACKGROUND The transistor is a key component of most integrated circuits. Since the drive current, and therefore speed, of a transistor is proportional to the gate width of the transistor, faster transistors generally require larger gate width. Thus, there is a trade-off between transistor size and speed, and “fin” field-effect transistors (finFETs) have been developed to address the conflicting goals of a transistor having maximum drive current and minimum size. FinFETs are characterized by a fin-shaped channel region that greatly increases the size of the transistor without significantly increasing the footprint of the transistor, and are now being applied in many integrated circuits. However, finFETs have their own drawbacks. As the feature sizes of transistor devices continue to shrink to achieve greater circuit density and higher performance, there is a need to improve transistor device structure to improve electrostatic coupling and reduce negative effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include a planar structure, a fin field effect transistor (FinFET) structure, and a gate-all-around (GAA) device structure. The GAA device structure, for example, includes several lattice matched channels suspended in a stacked configuration and connected by source/drain regions. The GAA device structure provides good electrostatic control and can find broad adoption in complementary metal oxide semiconductor (CMOS) wafer manufacturing. Logic gate performance is related to the characteristics of the materials used as well as the thickness and area of the structural layers. However, as some gate characteristics are adjusted to accommodate device scaling, challenges arise. For example, each cleaning step and each etch step of GAA device structure formation results in loss of spacer materials (i.e., inner, outer, and sidewall spacer materials). Typical processes for forming GAA device structures include removing a wafer from a processing tool, loading the wafers into a front opening unified pod (FOUP), using an OverHead Track (OHT) system to move the FOUP to a Stocker (stores the FOUP), using an OHT to move the FOUP back to the next processing tool, and loading the wafers into another processing tool (i.e., remove-load-move-move back-reload sequence). Typically, a cleaning process is performed before each step of the remove-load-move-move back-reload sequence performed in conventional cluster tools. As a result of the cleaning process performed before each step of the remove-load-move-move back-reload sequence, variation in the sidewall material is induced. Depositing additional sidewall material prior to cleaning and/or etching in attempt to compensate for the absolute value of the sidewall loss and variation in sidewall loss may negatively impact semiconductor device performance. Therefore, there is a need for improved methods and cluster tools for reducing the absolute value of the sidewall loss and the variation in sidewall loss in semiconductor device (e.g., GAA device structure) formation. SUMMARY One or more embodiments of the disclosure are directed a cluster tool for forming a gate-all-around (GAA) device. The cluster tool comprises a central transfer station configured to receive a substrate and to transfer the substrate to and from a plurality of processing chambers each independently connected to the central transfer station. The plurality of processing chambers comprises a first etch chamber configured to remove a dummy gate polysilicon layer from a top surface of a plurality of dummy gates. The plurality of dummy gates is formed from a substrate surface over a plurality of fins extending along a first direction to provide a plurality of trenches extending along a second direction crossing the first direction to expose portions of the plurality of fins so that portions of fins on the substrate surface are covered by the dummy gates and portions of the fins are exposed. The fins comprise alternating layers of a first material and a second material. The plurality of processing chambers comprises a second etch chamber configured to remove a dummy gate oxide material deposited on the plurality of fins and a third etch chamber configured to remove the layers of second material between adjacent layers of the first material. Additional embodiments of the disclosure are directed to a processing method. The processing method comprises rem