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US-12628617-B2 - Wafer chuck including self-sealing vacuum seal assemblies and methods for operating the same

US12628617B2US 12628617 B2US12628617 B2US 12628617B2US-12628617-B2

Abstract

A semiconductor processing apparatus includes a wafer chuck configured to hold a wafer on a top surface thereof. A plurality of lift-pin holes vertically extends through a chuck body of the wafer chuck. A plurality of lift pins are located in the plurality of lift-pin holes. A plurality of vacuum seal assemblies is located on a bottom portion of a respective one of the plurality of lift pins. Each vacuum seal assembly within the plurality of vacuum seal assemblies includes a respective set of ring segments that are configured to be assembled into a respective contiguous structure under a condition of an upward gas flow within a respective lift-pin hole selected from the plurality of lift-pin holes. Leaks in a vacuum seal between the wafer and the wafer chuck can be remedied by formation of at least one contiguous structure that provides an additional vacuum seal.

Inventors

  • Wei-Yu Tsai
  • Hung-Jui Kuo
  • Ming-Tan LEE

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Dates

Publication Date
20260512
Application Date
20230901

Claims (20)

  1. 1 . A semiconductor processing apparatus, comprising: a wafer chuck configured to hold a wafer on a top surface thereof; a plurality of lift-pin holes that vertically extend through a chuck body of the wafer chuck; a plurality of lift pins located in the plurality of lift-pin holes; a vacuum seal assembly laterally surrounding a bottom portion of a first lift pin among the plurality of lift pins, wherein a vacuum seal assembly within the plurality comprises: a confinement matrix structure including a vertically-extending opening aligned to an overlying lift-pin hole among the plurality of lift-pin holes and an annular cavity connected to, and laterally surrounding, the vertically-extending opening; and a set of ring segments located at least partly within the annular cavity and configured, in a sealing state, to assemble into a contiguous annulus that laterally surrounds and directly contacts the first lift pin and, in a non-sealing state, to be mutually spaced apart and out of contact with the first lift pin, wherein a positive pressure differential between a volume underlying the vacuum seal assembly and the overlying lift-pin hole induces an upward gas flow through the vertically-extending opening that drives the set of ring segments from the non-sealing state into the sealing state.
  2. 2 . The semiconductor processing apparatus of claim 1 , wherein the contiguous annulus remains as a contiguous structure under a condition of a full or partial vacuum within the lift-pin hole.
  3. 3 . The semiconductor processing apparatus of claim 1 , wherein the set of ring segments separates from one another to provide multiple disjoined structures under a condition of equal pressure between a volume inside the lift-pin hole and a volume underlying the set of ring segments.
  4. 4 . The semiconductor processing apparatus of claim 3 , wherein the set of ring segments moves downward and outward during a transition from the contiguous annulus to the multiple disjoined structures.
  5. 5 . The semiconductor processing apparatus of claim 1 , wherein the set of ring segments moves upward and inward during assembly into the contiguous structure annulus.
  6. 6 . The semiconductor processing apparatus of claim 1 , wherein the vacuum seal assembly is attached to a bottom surface of the wafer chuck.
  7. 7 . The semiconductor processing apparatus of claim 1 , wherein the top surface of the wafer chuck includes a plurality of vacuum grooves that is connected to vacuum pumping manifolds which are embedded in the wafer chuck, and wherein the contiguous annulus formed by the set of ring segments is maintained as long as at least one of the vacuum pumping manifolds is under vacuum.
  8. 8 . The semiconductor processing apparatus of claim 1 , wherein a volume fraction of the set of ring segments within the vertically-extending opening is greater in the sealing state than in the non-sealing state.
  9. 9 . A semiconductor processing apparatus, comprising: a wafer chuck configured to hold a wafer on a top surface thereof; a plurality of lift-pin holes that vertically extend through a chuck body of the wafer chuck; a plurality of lift pins located in the plurality of lift-pin holes; and vacuum seal assembly laterally surrounding a bottom portion of a lift pin among the plurality of lift pins, wherein the vacuum seal assembly comprises: a confinement matrix structure including a vertically-extending opening aligned to an overlying lift-pin hole among the plurality of lift-pin holes and an annular cavity connected to, and laterally surrounding, the vertically-extending opening, the confinement matrix structure comprising a contoured cap structure providing a first annular sloped sliding surface and a contoured base structure providing a second annular sloped sliding surface and a base opening through which the lift pin vertically extends, the contoured base structure being affixed to the contoured cap structure by at least one fastening element; and a set of ring segments located at least partly within the annular cavity and configured to form a contiguous structure annulus in a sealing state and to form multiple disjoined structures in a non-sealing state, the contiguous annulus laterally surrounding and contacting the lift pin; wherein a positive pressure differential between a volume underlying the vacuum seal assembly and the overlying lift-pin hole induces an upward gas flow through the vertically-extending opening that drives the set of ring segments from the non-sealing state into the sealing state; and wherein each ring segment includes an upper tapered sliding surface having a first taper angle α 1 with respect to a vertical direction and a lower tapered sliding surface having a second taper angle α 2 with respect to the vertical direction.
  10. 10 . The semiconductor processing apparatus of claim 9 , wherein: the lift pin vertically extends through the vertically-extending openings of a confinement matrix structure; each of the set of ring segments is in direct contact with a respective segment of a cylindrical sidewall of the lift pin in the sealing state; and each of the set of ring segments is not in direct contact with the lift pin in the non-sealing state.
  11. 11 . The semiconductor processing apparatus of claim 9 , wherein: the annular cavity is vertically bounded at top by a first annular sloping sliding surface that is configured to guide an inward-and-upward sliding movement of each ring segment during a transition into the sealing state; and the annular cavity is vertically bounded at bottom by a second annular sloping sliding surface that is configured to guide an outward-and-downward sliding movement of each ring segment during a transition to the non-sealing state.
  12. 12 . The semiconductor processing apparatus of claim 9 , wherein the confinement matrix structure comprises: a contoured cap structure including a first annular sloping sliding surface that tapers downward with a lateral distance from the vertically-extending opening; and a contoured base structure including an annular sloping top surface that tapers downward with the lateral distance from the vertically-extending opening.
  13. 13 . The semiconductor processing apparatus of claim 12 , wherein: the set of ring segments contacts the first annular sloping sliding surface and does not contact the second annular sloping sliding surface in the sealing state; and the set of ring segments contacts the second annular sloping sliding surface and does not contact the first annular sloping sliding surface in the non-sealing state.
  14. 14 . The semiconductor processing apparatus of claim 13 , wherein: the contoured base structure has a base opening; a lift pin vertically extends through the base opening; and the set of ring segments overlies more than 50% of a total area of the base opening that is not occupied by the lift pin while the set of ring segments is in the non-sealing state.
  15. 15 . A method of operating a semiconductor processing apparatus, the method comprising: providing a semiconductor processing apparatus comprising a wafer chuck configured to hold a wafer on a top surface thereof, wherein a plurality of lift-pin holes vertically extends through a chuck body of the wafer chuck, a plurality of lift pins are located in the plurality of lift-pin holes, and a vacuum seal assembly laterally surrounds a bottom portion of a first lift pin among the plurality of lift pins and includes a confinement matrix structure having a vertically-extending opening aligned to an overlying lift-pin hole and an annular cavity laterally surrounding the vertically-extending opening and a set of ring segments located at least partly within the annular cavity; disposing a wafer on the top surface of the wafer chuck; pulling the wafer toward the top surface of the wafer chuck by providing a vacuum suction on a backside of the wafer; and forming, in the vacuum seal assembly, a vacuum seal around the first lift pin by inducing, with a positive pressure differential between a volume underlying the vacuum seal assembly and the overlying lift-pin hole, an upward gas flow through the vertically-extending opening that drives the set of ring segments from a non-sealing state in which the ring segments are mutually spaced apart and out of contact with the first lift pin into a sealing state in which the ring segments assemble into a contiguous annulus that laterally surrounds and contacts the first lift pin.
  16. 16 . The semiconductor processing apparatus of claim 9 , wherein centers of curvature for the ring segments coincide in the sealing state and differ in the non-sealing state, and a radial offset between a first center and a second center corresponds to a difference between a second radius of curvature Rc 2 and a first radius of curvature Rc 1 that lies within 0.5 mm to 2.0 mm.
  17. 17 . The method of claim 15 , wherein the set of ring segments is assembled into the contiguous annulus by transfer of upward momentum to the set of ring segments during the upward gas flow through the vertically-extending opening.
  18. 18 . The method of claim 15 , wherein the set of ring segments is not in direct contact with one another, and is not in direct contact with the first lift pin prior to providing the vacuum suction on the backside of the wafer.
  19. 19 . The method of claim 15 , further comprising: performing a processing step on the wafer; and deactivating the vacuum suction on the backside of the wafer after performing the processing step on the wafer, wherein the contiguous annulus is transformed into a set of non-contacting discrete structures in which the set of ring segments is not in direct contact with one another and does not contact the first lift pin.
  20. 20 . The method of claim 15 , wherein: the semiconductor processing apparatus comprises a lithographic exposure apparatus that comprises: a laser system configured to generate a laser beam; an illumination optics system comprising a reticle therein and configured to guide the laser beam through the reticle; and a projection optics system located between the illumination optics system and the wafer chuck and configured to focus the laser beam onto a respective exposure field on the wafer; and the method further comprises lithographically exposing a photoresist layer on a top surface of the wafer after providing the vacuum suction on the backside of the wafer.

Description

BACKGROUND Warpage of wafers increases as the internal structures of packages become more complex. A wafer with high stiffness and negative warpage poses a challenge for vacuum systems due to formation of a non-negligible gap between the wafer and a wafer chuck, and resulting leakage in the vacuum suction. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a perspective view of an exemplary semiconductor processing apparatus including a wafer chuck according to an embodiment of the present disclosure. FIG. 2A is a vertical cross-sectional view a wafer chuck after loading a wafer on the wafer chuck and before lowering lift pins according to an embodiment of the present disclosure. FIG. 2B is a horizontal cross-sectional view of the wafer chuck along the horizontal plane B-B′ of FIG. 2A. The hinged vertical plane A-A′ is the cut plane of the vertical cross-sectional view of FIG. 2A. FIG. 2C is a horizontal cross-sectional view of the wafer chuck along the horizontal plane C-C′ of FIG. 2A. The hinged vertical plane A-A′ is the cut plane of the vertical cross-sectional view of FIG. 2A. FIG. 2D is a schematic vertical cross-sectional view of a gap between a wafer and lip seals in case of a severe wafer warpage. FIG. 3 is a vertical cross-sectional view of a wafer chuck after lowing the lift pins in embodiments in which no gap is present between the wafer and the wafer chuck after applying vacuum suction according to an embodiment of the present disclosure. FIG. 4 is a vertical cross-sectional view of the wafer chuck after lowering the lift pins in embodiments in which a gap is present between the wafer and the wafer chuck after applying vacuum suction according to an embodiment of the present disclosure. FIG. 5A is a top-down view of a vacuum seal assembly in which ring segments are disjoined from one another according to an aspect of the present disclosure. FIG. 5B is a vertical cross-sectional view of the vacuum seal assembly of FIG. 5A. FIG. 6A is a top-down view of a vacuum seal assembly in which ring segments are adjoined to one another to form a contiguous structure according to an aspect of the present disclosure. FIG. 6B is a vertical cross-sectional view of the vacuum seal assembly of FIG. 6A. FIG. 7A is a perspective view of a first exemplary set of ring segments according to an embodiment of the present disclosure. FIG. 7B is a perspective view of a second exemplary set of ring segments according to an embodiment of the present disclosure. FIG. 8A is a top-down view of a vacuum seal assembly in which ring segments are adjoined to one another to form a contiguous structure according to an aspect of the present disclosure. FIG. 8B is a vertical cross-sectional view of a ring segment in the vacuum seal assembly along the vertical plane B-B′ of FIG. 8A. FIG. 9 is a first flow chart illustrating a set of processing steps for implementing the methods of an embodiment of the present disclosure. FIG. 10 is a second flow chart illustrating a set of processing steps for implementing the methods of an embodiment of the present disclosure. FIG. 11 is a third flow chart illustrating a set of processing steps for implementing the methods of an embodiment of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Same reference numerals refer to the same element or similar elements, and a same material composition and a same function are presumed selected from elements with the same reference numeral unless otherwise stated explicitly. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be o