US-12628620-B1 - Die level integrated connection test circuit and method therefor

Abstract

In some embodiments, an integrated circuit (IC) chip package, includes a die; and die level diagnostic cell circuitry embedded in the die at a die level diagnostic testing location, wherein the die level diagnostic cell circuitry located at the die level diagnostic testing location incorporates a die level diagnostic stimulus to test a diagnostic trace of the die without requiring a decapsulation of the integrated circuit chip package. In some embodiments, the die level diagnostic cell circuitry is utilized to capture at least one of an inductance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace, a capacitance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace, an impedance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace, and a resistance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace.

Inventors

• Ahmad Byagowi
• Pradip Sairam Pichumani

Assignees

• META PLATFORMS, INC.

Dates

Publication Date

20260512

Application Date

20230413

Claims (19)

1. 1 . An integrated circuit chip package, comprising: a die; a printed circuit board (PCB); and die level diagnostic cell circuitry embedded in the die, wherein the die level diagnostic cell circuitry is configured to receive a die level diagnostic cell circuitry-based stimulus thorough a die level diagnostic cell circuitry stimulus driven diagnostic trace that extends through the die and into the PCB to test the die level diagnostic cell circuitry stimulus driven diagnostic trace without requiring a decapsulation of the integrated circuit chip package; wherein the die level diagnostic cell circuitry is utilized to capture a slew rate associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace.
2. 2 . The integrated circuit chip package of claim 1 , wherein: in order to test the die level diagnostic cell circuitry stimulus driven diagnostic trace of the integrated circuit chip package, the die level diagnostic cell circuitry-based stimulus is driven through the die level diagnostic cell circuitry stimulus driven diagnostic trace.
3. 3 . The integrated circuit chip package of claim 2 , wherein: the die level diagnostic cell circuitry-based stimulus is at least one of a time domain diagnostic stimulus or a frequency domain diagnostic stimulus.
4. 4 . The integrated circuit chip package of claim 3 , wherein: the die level diagnostic cell circuitry stimulus driven diagnostic trace includes at least one of transmission circuitry or reflection circuitry.
5. 5 . The integrated circuit chip package of claim 4 , wherein: die level diagnostic cell circuitry is embedded in the die at a corner location of the die.
6. 6 . The integrated circuit chip package of claim 5 , wherein: the die level diagnostic cell circuitry-based stimulus is driven through the die level diagnostic cell circuitry stimulus driven diagnostic trace to determine a failure onset.
7. 7 . The integrated circuit chip package of claim 6 , wherein: the die level diagnostic cell circuitry allows for a built-in approach to determine diagnostic characteristics associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace of the integrated circuit chip package.
8. 8 . The integrated circuit chip package of claim 7 , wherein: the die level diagnostic cell circuitry is utilized to ascertain at least one of an inductance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace, capacitance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace, an impedance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace, and a resistance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace.
9. 9 . A die, comprising: die level diagnostic cell circuitry embedded in the die, wherein the die level diagnostic cell circuitry is configured to receive a die level diagnostic cell circuitry-based stimulus thorough a die level diagnostic cell circuitry stimulus driven diagnostic trace that extends through the die and into a printed circuit board (PCB) coupled to the die to test the die level diagnostic cell circuitry stimulus driven diagnostic trace without requiring a decapsulation of an integrated circuit chip package including the die and the PCB; and wherein the die level diagnostic cell circuitry is utilized to capture a slew rate associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace.
10. 10 . The die of claim 9 , wherein: in order to test the die level diagnostic cell circuitry stimulus driven diagnostic trace, the die level diagnostic cell circuitry-based stimulus is driven through the die level diagnostic cell circuitry stimulus driven diagnostic trace.
11. 11 . The die of claim 10 , wherein: the die level diagnostic cell circuitry-based stimulus is at least one of a time domain diagnostic stimulus or a frequency domain diagnostic stimulus.
12. 12 . The die of claim 11 , wherein: the die level diagnostic cell circuitry stimulus driven diagnostic trace includes at least one of transmission circuitry or reflection circuitry.
13. 13 . The die of claim 12 , wherein: die level diagnostic cell circuitry is embedded in the die at a corner location of the die.
14. 14 . The die of claim 13 , wherein: the die level diagnostic cell circuitry-based stimulus is driven through the die level diagnostic cell circuitry stimulus driven diagnostic trace coupled to the die to determine a failure onset.
15. 15 . The die of claim 14 , wherein: the die level diagnostic cell circuitry allows for a built-in approach to determine diagnostic characteristics associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace coupled to the die.
16. 16 . The die of claim 15 , wherein: an impedance mismatch associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace is measured utilizing the die level diagnostic cell circuitry.
17. 17 . The die of claim 16 , wherein: the die level diagnostic cell circuitry is utilized to ascertain at least one of an inductance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace, a capacitance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace, an impedance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace, and a resistance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace.
18. 18 . An integrated circuit chip testing method, comprising: allocating an embedded portion of die circuitry of a die located in an integrated circuit chip package as die level diagnostic cell circuitry; generating a die level diagnostic cell circuitry-based stimulus at the die level diagnostic cell circuitry that is transmitted through a die level diagnostic cell circuitry stimulus driven diagnostic trace that extends through the die and into printed circuit board (PCB) of the integrated circuit chip package; utilizing the die level diagnostic cell circuitry-based stimulus and the die level diagnostic cell circuitry to test the die level diagnostic cell circuitry stimulus driven diagnostic trace without requiring a decapsulation of the integrated circuit chip package; and utilizing the die level diagnostic cell circuitry is utilized to capture a slew rate associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace.
19. 19 . The method of claim 18 , further comprising: utilizing the die level diagnostic cell circuitry to capture at least one of an inductance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace, a capacitance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace, an impedance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace, and a resistance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace.

Description

BACKGROUND Packaged semiconductor products are generally tested for quality control and functionality purposes in order to ship high-end semiconductor products to meet the current demands of customers. Generally, in order to test the packaged semiconductors, the packaged semiconductors are decapsulated in order to access and appropriately test dies and other components located inside the packaged semiconductors. Unfortunately, decapsulation and other destructive testing techniques utilized to test the internal components of the semiconductor package are not always desirable due to the prohibitive costs associated with performing decapsulation. Furthermore, the electrical properties of the components of the semiconductor package (e.g., dies, interconnects, packaging, and printed circuit boards (PCBs), etc.) are difficult to attain post assembly without utilizing costly external testing equipment. Therefore, a need exists to provide improved testing techniques for packaged semiconductors. SUMMARY This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Methods, systems, and computer readable mediums that store code for performing methods are described herein. In one aspect, an integrated circuit chip package, includes a die; and die level diagnostic cell circuitry embedded in the die at a die level diagnostic testing location. In some embodiments, the die level diagnostic cell circuitry is located at a corner location of the die and utilizes a die level diagnostic cell circuitry-based stimulus to test a die level diagnostic cell circuitry stimulus driven diagnostic trace of the integrated circuit chip package without requiring a decapsulation of the integrated circuit chip package. In some embodiments, the die level diagnostic cell circuitry is utilized to ascertain at least one of an inductance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace, a capacitance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace, an impedance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace, and a resistance associated with the die level diagnostic cell circuitry stimulus driven diagnostic trace. Further features and advantages of embodiments, as well as the structure and operation of various embodiments, are described in detail below with reference to the accompanying drawings. It is noted that the methods and systems are not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a block diagram of a diagnostic cell circuitry-configured integrated circuit (IC) chip package that includes die level diagnostic cell circuitry in accordance with some embodiments. FIG. 2 illustrates die level diagnostic cell circuitry-based diagnostic testing method performed utilizing the die level diagnostic cell circuitry of FIG. 1 in accordance with some embodiments. FIG. 3 illustrates an exemplary side view of example diagnostic cell circuitry-configured IC chip package used to implement the die level diagnostic cell circuitry-based diagnostic testing method of FIG. 2 in accordance with some embodiments. FIG. 4 illustrates an exemplary side view of an example diagnostic cell circuitry-configured IC chip package utilized to implement the die level diagnostic cell circuitry-based diagnostic testing method of FIG. 2 in accordance with some embodiments. FIG. 5 illustrates an exemplary side view of an example diagnostic cell circuitry-configured IC chip package utilized to implement the die level diagnostic cell circuitry-based diagnostic testing method of FIG. 2 in accordance with some embodiments. FIG. 6 illustrates an exemplary side view of an example diagnostic cell circuitry-configured IC chip package utilized to implement the die level diagnostic cell circuitry-based diagnostic testing method of FIG. 2 in accordance with some embodiments. FIG. 7 illustrates an exemplary side view of an example diagnostic cell circuitry-configured IC chip package utilized to implement the die level-based diagnostic testing method of FIG. 2 in accordance with some embodiments. FIG. 8 illustrates an exemplary side view of an example diagnostic cell circuitry-configured IC chip package utilized to implement the die level diagnostic cell circuitry-based diagnostic testing method of FIG. 2 in accordance with some embodiments. FIG. 9 illustrates an exemplary bottom-up view of an example die of a diagnostic cell circuitry-configured IC chip pac