US-12628622-B2 - Semiconductor chip having chamfer region for crack prevention

Abstract

A semiconductor chip including a guard ring that surrounds edges of a semiconductor substrate, an internal circuit structure that is formed on the semiconductor substrate and that includes a memory cell array region and a peripheral circuit region, and a crack detection circuit that is located between the guard ring and the internal circuit structure and that detects whether a crack occurs. The semiconductor chip further includes first to fourth chamfer regions having different shapes and sizes depending on the position of a pad or the design arrangement of the internal circuit structure.

Inventors

• Hyunhaeng Heo
• Sunghoon Kim
• JAEICK SON
• SeungYeon Kim

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20230131

Priority Date

20220728

Claims (20)

1. 1 . A semiconductor chip comprising: a guard ring surrounding edges of a semiconductor substrate; an internal circuit structure formed on the semiconductor substrate and including a memory cell array region and a peripheral circuit region; a crack detection circuit located between the guard ring and the internal circuit structure and configured to detect whether a crack occurs; a first chamfer region defined as an interior region of a right triangle with a first point, a second point, and a third point as vertices, wherein a first horizontal detection line and a first corner detection line of the crack detection circuit meet each other at the first point, the first corner detection line and a first vertical detection line of the crack detection circuit meet each other at the second point, and an extension line of the first horizontal detection line and an extension line of the first vertical detection line of the crack detection circuit meet each other at the third point; and a second chamfer region defined as an interior region of a right triangle with a fourth point, a fifth point, and a sixth point as vertices, wherein the first vertical detection line and a second corner detection line of the crack detection circuit meet each other at the fourth point, the second corner detection line and a second horizontal detection line of the crack detection circuit meet each other at the fifth point, and an extension line of the first vertical detection line and an extension line of the second horizontal detection line of the crack detection circuit meet each other at the sixth point, wherein a length between the fourth point and the sixth point of the second chamfer region differs from a length between the second point and the third point of the first chamfer region due to a pad located between the second horizontal detection line and the internal circuit structure.
2. 2 . The semiconductor chip of claim 1 , wherein the length between the fourth point and the sixth point of the second chamfer region is greater than the length between the second point and the third point of the first chamfer region.
3. 3 . The semiconductor chip of claim 1 , further comprising: a third chamfer region defined as an interior region of a right triangle with a seventh point, an eighth point, and a ninth point as vertices, wherein the second horizontal detection line and a third corner detection line of the crack detection circuit meet each other at the seventh point, the third corner detection line and a second vertical detection line of the crack detection circuit meet each other at the eighth point, and an extension line of the second horizontal detection line and an extension line of the second vertical detection line of the crack detection circuit meet each other at the ninth point, wherein a length between the fifth point and the sixth point of the second chamfer region differs from a length between the seventh point and the ninth point of the third chamfer region due to a design arrangement of the internal circuit structure.
4. 4 . The semiconductor chip of claim 3 , further comprising: a fourth chamfer region defined as an interior region of a right triangle with a tenth point, an eleventh point, and a twelfth point as vertices, wherein the second vertical detection line and a fourth corner detection line of the crack detection circuit meet each other at the tenth point, the fourth corner detection line and the first horizontal detection line of the crack detection circuit meet each other at the eleventh point, and an extension line of the second vertical detection line and an extension line of the first horizontal detection line of the crack detection circuit meet each other at the twelfth point, wherein a length between the eighth point and the ninth point of the third chamfer region differs from a length between the tenth point and the twelfth point of the fourth chamfer region due to the pad located between the second horizontal detection line and the internal circuit structure.
5. 5 . The semiconductor chip of claim 4 , wherein the length between the eighth point and the ninth point of the third chamfer region is greater than the length between the tenth point and the twelfth point of the fourth chamfer region.
6. 6 . The semiconductor chip of claim 5 , wherein a length between the first point and the third point of the first chamfer region differs from a length between the eleventh point and the twelfth point of the fourth chamfer region due to the design arrangement of the internal circuit structure.
7. 7 . The semiconductor chip of claim 6 , where a metal pattern structure is located in the first to fourth chamfer regions.
8. 8 . The semiconductor chip of claim 1 , wherein the internal circuit structure has a COP structure in which the memory cell array region is located on the peripheral circuit region, and wherein memory cells are stacked in a direction perpendicular to the semiconductor substrate in the memory cell array region.
9. 9 . The semiconductor chip of claim 8 , wherein in the memory cell array region, slopes of memory cells stacked in the direction perpendicular to the semiconductor substrate in the vicinity of the first horizontal detection line and the second horizontal detection line differ from each other due to a position of the pad.
10. 10 . The semiconductor chip of claim 9 , wherein a zone without transistors is located between the first horizontal detection line and the internal circuit structure.
11. 11 . The semiconductor chip of claim 1 , wherein magnitudes of interior angles at the first point and the second point of the first chamfer region differ from each other due to a design arrangement of the internal circuit structure.
12. 12 . A semiconductor chip comprising: a guard ring surrounding edges of a semiconductor substrate; an internal circuit structure formed on the semiconductor substrate and including a memory cell array region and a peripheral circuit region; a crack detection circuit located between the guard ring and the internal circuit structure and configured to detect whether a crack occurs; a first chamfer region defined as an interior region of a right triangle with a first point, a second point, and a third point as vertices, wherein a first horizontal detection line and a first corner detection line of the crack detection circuit meet each other at the first point, the first corner detection line and a first vertical detection line of the crack detection circuit meet each other at the second point, and an extension line of the first horizontal detection line and an extension line of the first vertical detection line of the crack detection circuit meet each other at the third point; a second chamfer region defined as an interior region of a right triangle with a fourth point, a fifth point, and a sixth point as vertices, wherein the first vertical detection line and a second corner detection line of the crack detection circuit meet each other at the fourth point, the second corner detection line and a second horizontal detection line of the crack detection circuit meet each other at the fifth point, and an extension line of the first vertical detection line and an extension line of the second horizontal detection line of the crack detection circuit meet each other at the sixth point; and first edge transistors located between main peripheral circuits of the peripheral circuit region and the second horizontal detection line; a pad between the second horizontal detection line and the internal circuit structure; and wherein a zone without transistors is located between the first horizontal detection line and the internal circuit structure, and magnitudes of interior angles at the first point and the second point of the first chamfer region differ from each other, and wherein magnitudes of interior angles at the fourth point and the fifth point of the second chamfer region differ from each other due to the first edge transistors and the pad.
13. 13 . The semiconductor chip of claim 12 , further comprising: wherein a length between the fourth point and the sixth point of the second chamfer region differs from a length between the second point and the third point of the first chamfer region due to the pad.
14. 14 . The semiconductor chip of claim 13 , wherein the internal circuit structure has a COP structure in which the memory cell array region is located on the peripheral circuit region, and wherein memory cells are stacked in a direction perpendicular to the semiconductor substrate in the memory cell array region.
15. 15 . The semiconductor chip of claim 12 , further comprising: second edge transistors between the main peripheral circuits of the peripheral circuit region and the first vertical detection line, wherein a length between the first point and the third point of the first chamfer region and a length between the fifth point and the sixth point of the second chamfer region are determined due to the second edge transistors.
16. 16 . The semiconductor chip of claim 15 , further comprising: a third chamfer region defined as an interior region of a right triangle with a seventh point, an eighth point, and a ninth point as vertices, wherein the second horizontal detection line and a third corner detection line of the crack detection circuit meet each other at the seventh point, the third corner detection line and a second vertical detection line of the crack detection circuit meet each other at the eighth point, and an extension line of the second horizontal detection line and an extension line of the second vertical detection line of the crack detection circuit meet each other at the ninth point; a fourth chamfer region defined as an interior region of a right triangle with a tenth point, an eleventh point, and a twelfth point as vertices, wherein the second vertical detection line and a fourth corner detection line of the crack detection circuit meet each other at the tenth point, the fourth corner detection line and the first horizontal detection line of the crack detection circuit meet each other at the eleventh point, and an extension line of the second vertical detection line and an extension line of the first horizontal detection line of the crack detection circuit meet each other at the twelfth point; and third edge transistors between the main peripheral circuits of the peripheral circuit region and the second vertical detection line, wherein a length between the seventh point and the ninth point of the third chamfer region and a length between the eleventh point and the twelfth point of the fourth chamfer region are determined due to the third edge transistors.
17. 17 . A semiconductor chip comprising: an upper chip including a memory cell array region; and a lower chip including a peripheral circuit region, the lower chip being connected to the upper chip by a bonding method, wherein each of the upper chip and the lower chip includes: a guard ring configured to surround edges of a semiconductor substrate; an internal circuit structure formed on the semiconductor substrate, the internal circuit structure including the memory cell array region or the peripheral circuit region; and a crack detection circuit located between the guard ring and the internal circuit structure and configured to detect whether a crack occurs, wherein the semiconductor chip further comprises: a first chamfer region defined as an interior region of a right triangle with a first point, a second point, and a third point as vertices, wherein a first horizontal detection line and a first corner detection line of the crack detection circuit meet each other at the first point, the first corner detection line and a first vertical detection line of the crack detection circuit meet each other at the second point, and an extension line of the first horizontal detection line and an extension line of the first vertical detection line of the crack detection circuit meet each other at the third point; and a second chamfer region defined as an interior region of a right triangle with a fourth point, a fifth point, and a sixth point as vertices, wherein the first vertical detection line and a second corner detection line of the crack detection circuit meet each other at the fourth point, the second corner detection line and a second horizontal detection line of the crack detection circuit meet each other at the fifth point, and an extension line of the first vertical detection line and an extension line of the second horizontal detection line of the crack detection circuit meet each other at the sixth point, and wherein a length between the fourth point and the sixth point of the second chamfer region is greater than a length between the second point and the third point of the first chamfer region due to a pad located between the second horizontal detection line and the internal circuit structure.
18. 18 . The semiconductor chip of claim 17 , further comprising: a third chamfer region defined as an interior region of a right triangle with a seventh point, an eighth point, and a ninth point as vertices, wherein the second horizontal detection line and a third corner detection line of the crack detection circuit meet each other at the seventh point, the third corner detection line and a second vertical detection line of the crack detection circuit meet each other at the eighth point, and an extension line of the second horizontal detection line and an extension line of the second vertical detection line of the crack detection circuit meet each other at the ninth point, wherein a length between the fifth point and the sixth point of the second chamfer region differs from a length between the seventh point and the ninth point of the third chamfer region due to a design arrangement of the internal circuit structure.
19. 19 . The semiconductor chip of claim 18 , further comprising: a fourth chamfer region defined as an interior region of a right triangle with a tenth point, an eleventh point, and a twelfth point as vertices, wherein the second vertical detection line and a fourth corner detection line of the crack detection circuit meet each other at the tenth point, the fourth corner detection line and the first horizontal detection line of the crack detection circuit meet each other at the eleventh point, and an extension line of the second vertical detection line and an extension line of the first horizontal detection line of the crack detection circuit meet each other at the twelfth point, wherein a length between the eighth point and the ninth point of the third chamfer region differs from a length between the tenth point and the twelfth point of the fourth chamfer region due to the pad located between the second horizontal detection line and the internal circuit structure.
20. 20 . The semiconductor chip of claim 17 , wherein a zone without transistors is located between the first horizontal detection line and the internal circuit structure.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0094216 filed on Jul. 28, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND Embodiments of the present disclosure described herein relate to a semiconductor chip, and more particularly, relate to a semiconductor chip having chamfer regions for preventing cracks in corners thereof. Semiconductor chips are manufactured through a die sawing process of cutting a semiconductor wafer. During the die sawing process, the semiconductor wafer is cut along scribe lane regions by a sawing blade, and thus the semiconductor chips are physically separated from one another. As high-capacity and high-integration integrated circuit elements are required, the area occupied by the scribe lane regions in the semiconductor wafer is reduced. Due to stress applied to a semiconductor chip during a die sawing process, a risk of damage to an integrated circuit element increases. In particular, there is a high risk of damage to chamfer regions that are four corners of the semiconductor chip. The chamfer regions, which are chamfered corner portions between a guard ring and a crack detection circuit, may include a metal pattern structure. The metal pattern structure may prevent crack propagation that is likely to occur in the die sawing process and may reduce defects of an internal circuit structure. In general, the chamfer regions of the semiconductor chip have the same shape and size at the four corners of the semiconductor chip. The chamfer regions may have the shape of a right triangle in the corner portions of the semiconductor chip. However, in the semiconductor chip, the design arrangement of the internal circuit structure or the position of a pad may be changed according to the development of process and design technologies. Accordingly, a semiconductor chip needs to be designed to have, at four corners thereof, chamfer regions having different shapes and sizes. SUMMARY Embodiments of the present disclosure provide a semiconductor chip including chamfer regions having different shapes and sizes depending on the design arrangement of an internal circuit structure or the position of a pad. According to example embodiments, a semiconductor device includes a guard ring surrounding edges of a semiconductor substrate; an internal circuit structure formed on the semiconductor substrate and including a memory cell array region and a peripheral circuit region; a crack detection circuit located between the guard ring and the internal circuit structure and configured to detect whether a crack occurs; a first chamfer region defined as an interior region of a right triangle with a first point, a second point, and a third point as vertices, wherein a first horizontal detection line and a first corner detection line of the crack detection circuit meet each other at the first point, the first corner detection line and a first vertical detection line of the crack detection circuit meet each other at the second point, and an extension line of the first horizontal detection line and an extension line of the first vertical detection line of the crack detection circuit meet each other at the third point; and a second chamfer region defined as an interior region of a right triangle with a fourth point, a fifth point, and a sixth point as vertices, wherein the first vertical detection line and a second corner detection line of the crack detection circuit meet each other at the fourth point, the second corner detection line and a second horizontal detection line of the crack detection circuit meet each other at the fifth point, and an extension line of the first vertical detection line and an extension line of the second horizontal detection line of the crack detection circuit meet each other at the sixth point, wherein a length between the fourth point and the sixth point of the second chamfer region differs from a length between the second point and the third point of the first chamfer region due to a pad located between the second horizontal detection line and the internal circuit structure. According to example embodiments, a semiconductor device includes a guard ring surrounding edges of a semiconductor substrate; an internal circuit structure formed on the semiconductor substrate and including a memory cell array region and a peripheral circuit region; a crack detection circuit located between the guard ring and the internal circuit structure and configured to detect whether a crack occurs; a first chamfer region defined as an interior region of a right triangle with a first point, a second point, and a third point as vertices, wherein a first horizontal detection line and a first corner detection line of the crack detection circuit meet each other at the first point, the first corner detection line and a first vertical detect