US-12628624-B2 - Manufacturing method for forming semiconductor device

Abstract

The method includes performing a well implantation process to dope a dopant into a semiconductor substrate; after performing the well implantation process, performing a flash anneal on the semiconductor substrate, the flash anneal including a first preheat step and a first annealing step after the first preheat step, the first preheat step performed at a preheat temperature ranging from about 200° C. to about 800° C., the first annealing step having a peak temperature ramp profile, the peak temperature ramp profile having a peak temperature ranging from about 1000° C. to about 1200° C.; after performing the flash anneal, performing a rapid thermal anneal (RTA) on the semiconductor substrate, the RTA including a second preheat step, the first preheat step of the flash anneal being performed for a shorter duration than the second preheat step of the RTA.

Inventors

• Jhih-Yong HAN
• Wen-Yen Chen
• Po-Kang Ho
• Tsai-Yu Huang
• Huicheng Chang
• Yee-Chia Yeo

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260512

Application Date

20220215

Claims (20)

1. 1 . A method, comprising: performing a well implantation process to dope a dopant into a semiconductor substrate; after performing the well implantation process, performing a flash anneal on the semiconductor substrate, the flash anneal including a first preheat step and a first annealing step after the first preheat step, the first preheat step performed at a preheat temperature ranging from about 200° C. to about 800° C., the first annealing step having a peak temperature ramp profile, the peak temperature ramp profile having a peak temperature ranging from about 1000° C. to about 1200° C.; after performing the flash anneal, performing a rapid thermal anneal (RTA) on the semiconductor substrate, the RTA including a second preheat step, the first preheat step of the flash anneal being performed for a shorter duration than the second preheat step of the RTA; and forming a gate structure over the semiconductor substrate, wherein the RTA is performed prior to forming the gate structure.
2. 2 . The method of claim 1 , wherein the first preheat step has a temperature ramp-up rate ranging from about 10 to about 150° C./s.
3. 3 . The method of claim 1 , wherein the preheat temperature is less than about 700° C.
4. 4 . The method of claim 1 , wherein the peak temperature is greater than about 1100° C.
5. 5 . The method of claim 1 , wherein the RTA includes a second annealing step having a spike temperature ramp profile, the spike temperature ramp profile has a spike temperature ranging from about 1000° C. to about 1200° C.
6. 6 . The method of claim 5 , wherein the spike temperature ramp profile of the RTA has a duration ranging from about 1 to about 500 seconds.
7. 7 . The method of claim 1 , further comprising: forming an oxide layer after implanting the dopant and prior to performing the flash anneal.
8. 8 . A method, comprising: implanting a dopant into a semiconductor substrate; after implanting the dopant, performing a first anneal on the semiconductor substrate, the first anneal including a first preheat step and a first annealing step after the first preheat step, the first preheat step performed at a preheat temperature ranging from about 200° C. to about 800° C., wherein a time period performed at a temperature higher than about 700° C. for the first preheat step is less than about 10 seconds, the first annealing step has a peak temperature ramp profile, the peak temperature ramp profile has a peak temperature ranging from about 1000° C. to about 1200° C.; and after performing the first anneal, performing a second anneal on the semiconductor substrate, the second anneal including a second preheat step and a second annealing step after the second preheat step, the second annealing step having a spike temperature ramp profile, the spike temperature ramp profile having a spike temperature ranging from about 1000° C. to about 1200° C., and a highest temperature in the second preheat step of the second anneal is lower than a highest temperature in the first preheat step of the first anneal.
9. 9 . The method of claim 8 , wherein the first preheat step of the first anneal is performed for a shorter duration than the second preheat step of the second anneal.
10. 10 . The method of claim 9 , wherein the second preheat step of the second anneal is performed at the temperature lower than about 700° C.
11. 11 . The method of claim 8 , wherein the first anneal is a flash anneal, and the second anneal is a rapid thermal anneal.
12. 12 . The method of claim 8 , further comprising: after performing the second anneal, forming epitaxial nanosheet channels over the semiconductor substrate; and forming a gate structure wrapping around the epitaxial nanosheet channels.
13. 13 . A method, comprising: forming an oxide layer over a semiconductor substrate; implanting a dopant into the semiconductor substrate through the oxide layer; after implanting the dopant, performing a first anneal on the semiconductor substrate, the first anneal including a first annealing step having a peak temperature ramp profile, the peak temperature ramp profile having a peak temperature ranging from about 1000° C. to about 1200° C.; after performing the first anneal, performing a second anneal on the semiconductor substrate, the second anneal including a second annealing step having a spike temperature ramp profile, the spike temperature ramp profile having a spike temperature ranging from about 1000° C. to about 1200° C.; and forming a gate structure over the semiconductor substrate, wherein the second anneal is performed prior to forming the gate structure.
14. 14 . The method of claim 13 , wherein the first anneal includes a preheat step performing before the first annealing step, the preheat step is performed at a preheat temperature ranging from about 200° C. to about 800° C., and a time period performed at a temperature above about 700° C. for the preheat step is less than about 10 seconds.
15. 15 . The method of claim 13 , wherein the first anneal further includes a first preheat step performed before the first annealing step, the second anneal further includes a second preheat step performed before the second annealing step, and the first preheat step of the first anneal is performed for a shorter duration than the second preheat step of the second anneal.
16. 16 . The method of claim 13 , wherein the peak temperature ramp profile of the first anneal has a half maximum full width ranging from about 1.5 to about 2.5 milliseconds.
17. 17 . The method of claim 13 , further comprising: after performing the second anneal, removing the oxide layer by using a wet etching process.
18. 18 . The method of claim 1 , wherein a highest temperature in the second preheat step of the RTA is lower than a highest temperature in the first preheat step of the flash anneal.
19. 19 . The method of claim 8 , further comprising: forming an oxide layer after implanting the dopant and prior to performing the first anneal.
20. 20 . The method of claim 13 , wherein the first anneal further includes a first preheat step performed before the first annealing step, the second anneal further includes a second preheat step performed before the second annealing step, and a highest temperature in the second preheat step of the second anneal is lower than a highest temperature in the first preheat step of the first anneal.

Description

BACKGROUND Semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates an example of a nanostructure field-effect transistor (nano-FET) in a three-dimensional view, in accordance with some embodiments. FIGS. 2A and 2B are a flowchart of a method for forming a semiconductor device in accordance with some embodiments of the present disclosure. FIGS. 3A, 4A, 5A, 6, 7A, 7B, 8, 9, 10, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, and 16B illustrate a method in various stages of forming a semiconductor device in accordance with some embodiments of the present disclosure. FIGS. 3B and 4B illustrate schematic plan-view transmission electron microscopy (PVTEM) images showing extended defect evolutions on a substrate after well implantation processes and prior to an annealing process in accordance with some embodiments of the present disclosure. FIGS. 5B and 5C illustrate schematic temperature-time profiles of annealing processes in accordance with some embodiments of the present disclosure. FIGS. 5D and 5E illustrate schematic PVTEM images showing extended defect evolutions on substrates after annealing processes in accordance with some embodiments of the present disclosure. FIG. 5F illustrates experimental results showing different annealing conditions on a substrate effect on activation (Rs) versus junction depth (Xj) of dopants in the substrate in accordance with some embodiments of the present disclosure. FIG. 5G illustrates experimental results showing different annealing conditions on a substrate effect on concentration (atom/cm3) versus mobility (cm2/Vs) of dopants in the substrate in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, “around,” “about,” “approximately,” or “substantially” may mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range. One skilled in the art will realize, however, that the value or range recited throughout the description are merely examples, and may be reduced with t