US-12628626-B2 - Three-dimensional memory device and method

US12628626B2US 12628626 B2US12628626 B2US 12628626B2US-12628626-B2

Abstract

A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric.

Inventors

Han-Jong Chia
Meng-Han LIN
Sheng-Chen Wang
Feng-Cheng Yang
Chung-Te Lin

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20240524

Claims (20)

1 . A semiconductor device comprising: a substrate; a layer stack over the substrate, wherein the layer stack comprises a plurality of dielectric layers and a plurality of word lines (WLs) interleaved with the plurality of dielectric layers; a dielectric structure extending vertically through the layer stack from a lower surface of the layer stack facing the substrate to an upper surface of the layer stack distal from the substrate; a channel material around and contacting the dielectric structure; a bit line (BL) and a source line (SL) that extend vertically through the layer stack, wherein the BL extends along a first sidewall of the channel material, wherein the SL extends along a second sidewall of the channel material opposing the first sidewall; and a ferroelectric material extending vertically through the layer stack, wherein a first portion of the ferroelectric material extends along a third sidewall of the channel material, wherein a second portion of the ferroelectric material extends along a fourth sidewall of the channel material opposing the third sidewall.
2 . The semiconductor device of claim 1 , wherein the BL and the SL are in contact with the first sidewall and the second sidewall of the channel material, respectively.
3 . The semiconductor device of claim 2 , wherein the first portion and the second portion of the ferroelectric material are in contact with the third sidewall and the fourth sidewall of the channel material, respectively.
4 . The semiconductor device of claim 1 , wherein in a top view, the BL and the SL extend continuously from the first portion of the ferroelectric material to the second portion of the ferroelectric material.
5 . The semiconductor device of claim 4 , wherein in the top view, the dielectric structure and the channel material are disposed within an area delimited by the BL, the SL, the first portion of the ferroelectric material, and the second portion of the ferroelectric material.
6 . The semiconductor device of claim 5 , wherein a third portion of the ferroelectric material extends along a lower surface of the channel material facing the substrate.
7 . The semiconductor device of claim 1 , wherein an upper portion of the dielectric structure distal from the substrate is wider than a lower portion of the dielectric structure proximate to the substrate.
8 . The semiconductor device of claim 7 , wherein the channel material extends along a surface of the lower portion of the dielectric structure facing the substrate.
9 . The semiconductor device of claim 8 , wherein the ferroelectric material extends along a lower surface of the channel material facing the substrate, wherein a sidewall of the channel material facing the dielectric structure is flush with a sidewall of the ferroelectric material facing the dielectric structure.
10 . The semiconductor device of claim 1 , further comprising a dielectric material extending vertically from the upper surface of the layer stack toward the lower surface of the layer stack, wherein the dielectric material extends from the first portion of the ferroelectric material to the second portion of the ferroelectric material.
11 . The semiconductor device of claim 10 , wherein the ferroelectric material contacts and extends along a first sidewall of the dielectric material, a second opposing sidewall of the dielectric material, and a lower surface of the dielectric material facing the substrate.
12 . A semiconductor device comprising: a layer stack over a substrate, wherein the layer stack comprises a plurality of dielectric layers interleaved with a plurality of word lines (WLs); a dielectric plug extending vertically through the layer stack; a ferroelectric material extending vertically through the layer stack, wherein the dielectric plug is disposed between a first portion of the ferroelectric material and a second portion of the ferroelectric material; a channel material around and contacting the dielectric plug, wherein the channel material extends from the first portion of the ferroelectric material to the second portion of the ferroelectric material; and a bit line (BL) and a source line (SL) extending vertically through the layer stack and between the first portion of the ferroelectric material and the second portion of the ferroelectric material, wherein the BL extends along a first sidewall of the channel material, wherein the SL extends along a second sidewall of the channel material opposing the first sidewall of the channel material.
13 . The semiconductor device of claim 12 , wherein the BL and the SL contact and extend along the first sidewall of the channel material and the second sidewall of the channel material, respectively.
14 . The semiconductor device of claim 13 , wherein the ferroelectric material contacts and extends along a third sidewall of the channel material and a fourth sidewall of the channel material opposing the third sidewall of the channel material.
15 . The semiconductor device of claim 12 , further comprising a dielectric material embedded in the layer stack, wherein the dielectric material is disposed between the first portion of the ferroelectric material and the second portion of the ferroelectric material, wherein in a top view, the SL, the BL, the dielectric plug, and the channel material are disposed between a first portion of the dielectric material and a second portion of the dielectric material.
16 . The semiconductor device of claim 15 , wherein the first portion of the dielectric material contacts and extends along a sidewall of the BL facing away from the dielectric plug, and a second portion of the dielectric material contacts and extends along a sidewall of the SL facing away from the dielectric plug.
17 . The semiconductor device of claim 12 , wherein a WL of the plurality of WLs comprises: a conductive material; and a liner material, wherein the liner material comprises: a first portion extending along an upper surface of the conductive material facing away from the substrate; a second portion extending along a lower surface of the conductive material facing the substrate; and a third portion extending from the upper surface of the conductive material to the lower surface of the conductive material, wherein the third portion of the liner material is thicker than the first portion of the liner material and the second portion of the liner material.
18 . A semiconductor device comprising: a layer stack over a substrate, wherein the layer stack comprises a plurality of dielectric layers and a plurality of conductive features interleaved with the plurality of dielectric layers; a dielectric plug embedded in the layer stack and extending vertically through the layer stack; a bit line (BL) and a source line (SL) that extend vertically through the layer stack, wherein the BL and the SL extend along a first sidewall of the dielectric plug and a second opposing sidewall of the dielectric plug, respectively; a ferroelectric material extending vertically through the layer stack, wherein a first portion of the ferroelectric material and a second portion of the ferroelectric material extend along a third sidewall of the dielectric plug and a fourth opposing sidewall of the dielectric plug, respectively; and a channel material encircling and contacting sidewalls of the dielectric plug, wherein the channel material is disposed between the ferroelectric material and the dielectric plug, between the BL and the dielectric plug, and between the SL and the dielectric plug.
19 . The semiconductor device of claim 18 , wherein in a top view, the channel material fills spaces between the ferroelectric material and the dielectric plug, between the BL and the dielectric plug, and between the SL and the dielectric plug.
20 . The semiconductor device of claim 18 , wherein a conductive feature of the plurality of conductive features comprises: a conductive material; and a liner material, wherein the liner material comprises: a first portion extending along an upper surface of the conductive material distal from the substrate; and a second portion extending through the conductive material and separating the conductive material into separate portions, wherein the second portion of the liner material is thicker than the first portion of the liner material.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application is a continuation of U.S. patent application Ser. No. 17/814,626, filed Jul. 25, 2022 and entitled “Three-Dimensional Memory Device and Method,” which is a divisional of U.S. patent application Ser. No. 16/951,595, filed Nov. 18, 2020 and entitled “Three-Dimensional Memory Device and Method,” now U.S. Pat. No. 11,587,823, issued Feb. 21, 2023, which claims the benefit of U.S. Provisional Application No. 63/045,274, filed on Jun. 29, 2020, which applications are hereby incorporated herein by reference. BACKGROUND Semiconductor memories are used in integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. Semiconductor memories include two major categories. One is volatile memories; the other is non-volatile memories. Volatile memories include random access memory (RAM), which can be further divided into two sub-categories, static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they will lose the information they store when they are not powered. On the other hand, non-volatile memories can keep data stored on them without power being supplied. One type of non-volatile semiconductor memory is ferroelectric random access memory (FeRAM, or FRAM). Advantages of FeRAM include its fast write/read speed and small size. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a cross-sectional view of a semiconductor device with integrated memory devices, in an embodiment. FIGS. 2-18 and 19A-19F illustrate various views of a three-dimensional (3D) ferroelectric random access memory (FeRAM) device at various stages of manufacturing, in an embodiment. FIGS. 20 and 21 illustrate cross-sectional views of a three-dimensional (3D) ferroelectric random access memory (FeRAM) device at various stages of manufacturing, in another embodiment. FIG. 22 illustrates a top view of a three-dimensional (3D) ferroelectric random access memory (FeRAM) device, in yet another embodiment. FIG. 23 illustrates a flow chart of a method of forming a three-dimensional (3D) memory device, in some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Throughout the discussion herein, unless otherwise specified, the same or similar reference numeral in different figures refers to the same or similar element formed by a same or similar process using a same or similar material(s). In some embodiments, a channel-last method for forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack comprising alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending through the third dielectric material; removing portions of the third dielectric material disposed between respective BLs and SLs to form openings in the third dielectric material; forming a channel material along sidewalls of the openings; and filling the openings with a fourth