US-12628628-B2 - Structure and method to improve FAV RIE process margin and electromigration

Abstract

A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.

Inventors

• Benjamin David Briggs
• Joe Lee
• Theodorus Eduardus Standaert

Assignees

• ADEIA SEMICONDUCTOR SOLUTIONS LLC

Dates

Publication Date

20260512

Application Date

20240529

Claims (20)

1. 1 . A semiconductor device, comprising: a lower interconnect level comprising a first interlevel dielectric, ILD, and a plurality of parallel lower metal lines in an upper portion of the first ILD; an upper interconnect level comprising a second ILD and an upper metal line in an upper portion of the second ILD; a self-aligned via connecting the upper metal line to a first lower metal line, wherein: the first ILD comprises a first ILD region disposed between the first lower metal line and an adjacent second lower metal line; the second ILD comprises a second ILD region disposed on the first ILD region; the first ILD region comprises a first material and the second ILD region comprises a second material different than the first material; the first material is disposed adjacent to an interface between the first ILD region and the second ILD region and the second material is disposed adjacent to the same interface; the second ILD region comprises opposing vertically-oriented sidewalls self-aligned to opposing vertically-oriented sidewalls of the first ILD region therebelow and separated by a distance less than a distance separating opposing vertically-oriented sidewalls of the first ILD region; and the self-aligned via contacts the second ILD region.
2. 2 . The semiconductor device of claim 1 , wherein the self-aligned via is wider at its interface with the upper metal line than at its interface with the first lower metal line.
3. 3 . The semiconductor device of claim 1 , wherein a vertically-oriented sidewall of an upper portion of the self-aligned via is disposed over the second ILD region.
4. 4 . The semiconductor device of claim 1 , wherein: a lower portion of the self-aligned via is disposed between opposing portions of a liner, and one of the opposing portions of the liner is disposed on one of the vertically-oriented sidewalls of the second ILD region.
5. 5 . The semiconductor device of claim 4 , wherein the lower portion of the self-aligned via fully contacts an entire width of the lower metal line.
6. 6 . The semiconductor device of claim 1 , wherein the self-aligned via contacts one of the vertically-oriented sidewalls of the second ILD region.
7. 7 . The semiconductor device of claim 1 , wherein an upper surface of the first ILD region is substantially co-planar with an upper surface of the first lower metal line.
8. 8 . The semiconductor device of claim 1 , wherein the distance between the vertically-oriented sidewalls of the second ILD region is defined directly above the interface.
9. 9 . The semiconductor device of claim 1 , wherein the distance between the vertically-oriented sidewalls of the first ILD region is defined directly below the interface.
10. 10 . The semiconductor device of claim 1 , wherein: the distance between the vertically-oriented sidewalls of the second ILD region is defined directly above the interface; and the distance between the vertically-oriented sidewalls of the first ILD region is defined directly below the interface.
11. 11 . The semiconductor device of claim 1 , wherein a liner is disposed on portions of the vertically-oriented sidewalls of the second ILD region.
12. 12 . The semiconductor device of claim 11 , wherein a lower portion of the self-aligned via fully contacts an entire width of the lower metal line.
13. 13 . The semiconductor device of claim 11 , wherein: a lower portion of the self-aligned via is disposed between opposing portions of the liner; and one of the opposing portions of the liner is disposed on one of the vertically-oriented sidewalls of the second ILD region.
14. 14 . The semiconductor device of claim 13 , wherein the lower portion of the self-aligned via fully contacts an entire width of the lower metal line.
15. 15 . The semiconductor device of claim 11 , wherein the liner comprises nitride.
16. 16 . The semiconductor device of claim 1 , wherein the self-aligned via contacts a substantially horizontal portion of the second ILD region.
17. 17 . The semiconductor device of claim 16 , wherein: the second ILD region is disposed on a first side of the self-aligned via; and the self-aligned via further contacts a substantially horizontal portion of another second ILD region disposed on a second side of the self-aligned via opposite to the first side.
18. 18 . The semiconductor device of claim 1 , wherein the plurality of parallel lower metal lines comprise Cu.
19. 19 . The semiconductor device of claim 1 , wherein the self-aligned via comprises Cu.
20. 20 . The semiconductor device of claim 1 , wherein the upper metal line comprises Cu.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application is a continuation of U.S. patent application Ser. No. 18/205,178, filed Jun. 2, 2023, which is a continuation of U.S. patent application Ser. No. 17/212,267, filed Mar. 25, 2021, now U.S. Pat. No. 11,710,658, which is a continuation of U.S. patent application Ser. No. 15/852,151, filed on Dec. 22, 2017, now U.S. Pat. No. 10,985,056, which is a continuation of U.S. patent application Ser. No. 15/335,122, filed on Oct. 26, 2016, now U.S. Pat. No. 9,953,865, the entire contents of which are hereby incorporated by reference in their entireties. BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to a method, system, and apparatus for a semiconductor using fully aligned via (FAV) reactive ion etching (RIE), and more particularly relates to a method, system, and apparatus to improve FAV RIE process margin and Electromigration resistance. Description of the Related Art The fabrication of Very-Large Scale Integrated (VISI) requires an interconnect structure including metallic wiring that connects individual devices in a single semiconductor chip. With the chip being massively reduced in size over the years, the interconnect structure has also been reduced accordingly. The via levels are one of the most challenging to print. Additionally, there are overlay errors that result from misalignment during the lithography. The overlay errors may lead to reliability issues. A failure for interconnects that may be dependent on overlay error of lithographic patterns, are electromigration (EM) and time-dependent dielectric breakdown (TDDB). Overlay errors in the related art result in reduced spacing between the via and the metal level below, and therefore increase the dielectric field. There is a need to provide a technique of reducing the spacing variation. There is a need to providing a technique of forming a fully aligned via that is more efficient and avoids affecting yield and reliability issues such that there is an improvement in process margin and Electromigration resistance. SUMMARY OF INVENTION In view of the foregoing and other problems, disadvantages, and drawbacks of the aforementioned background art, an exemplary aspect of the present invention provides a system, apparatus, and method of providing a method, system, and apparatus to improve FAV RIF process margin and Electromigration resistance. One aspect of the present invention provides a method of forming fully aligned vias in a semiconductor device. The method includes forming an Mx level interconnect line embedded in an Mx interlevel dielectric (ILD). The Mx level interconnect line is recessed below the Mx interlevel dielectric or a dielectric is selectively deposited on the Mx interlevel dielectric. The method also includes laterally etching the exposed upper portion of the Mx interlevel dielectric bounding the recess or laterally etching the selectively deposited dielectric. The method further includes depositing a dielectric cap layer and an Mx+1 level interlevel dielectric on top of the Mx interlevel dielectric and forming a via opening. Another aspect of the present invention provides a semiconductor device including an Mx interlevel dielectric (ILD), an Mx level interconnect line embedded in the Mx interlevel dielectric, and an Mx+1 level ILD formed on the Mx interlevel dielectric and the Mx level interconnect line. The Mx interconnect line is recessed below the Mx interlevel dielectric. The Mx interlevel dielectric includes an exposed upper portion bounding the recess, a dielectric cap layer deposited on the Mx interlevel dielectric, and the Mx level interconnect line. Yet another aspect of the present invention provides a semiconductor device including an Mx interlevel dielectric (ILD), an Mx level interconnect line embedded in the Mx interlevel dielectric, a dielectric layer selectively formed on the Mx interlevel dielectric and laterally etched to bound a via, a dielectric cap layer, and an Mx+1 level ILD. The dielectric cap layer is deposited on the Mx interlevel dielectric, the via, the Mx level interconnect line, and the dielectric layer. The Mx+1 level ILD is formed on the Mx interlevel dielectric, the dielectric layer, and the Mx level interconnect line. There has thus been outlined, rather broadly, certain embodiments of the invention in order that the detailed description thereof herein may be better understood, and in order that the present contribution to the art may be better appreciated. There are, of course, additional embodiments of the invention that will be described below and which will form the subject matter of the claims appended hereto. BRIEF DESCRIPTION OF DRAWINGS The exemplary aspects of the invention will be better understood from the following detailed description of the exemplary embodiments of the invention with reference to the drawings. FIG. 1A illustrates a FAV RIE of the related art. FIG. 1B illustrates a further proc