US-12628629-B2 - Via opening rectification using lamellar triblock copolymer, polymer nanocomposite, or mixed epitaxy

US12628629B2US 12628629 B2US12628629 B2US 12628629B2US-12628629-B2

Abstract

Methods for forming via openings by using a lamellar triblock copolymer, a polymer nanocomposite, and a mixed epitaxy approach are disclosed. An example method includes forming a guiding pattern (e.g., a topographical guiding pattern, chemical guiding pattern, or mixed guiding pattern) on a surface of a layer of an IC device, forming lamellar structures based on the guiding pattern by using the lamellar triblock copolymer or forming cylindrical structures based on the guiding pattern by using the polymer nanocomposite, and forming via openings by removing a lamella from each of at least some of the lamellar structures or removing a nanoparticle from each of at least some of the cylindrical structures.

Inventors

Gurpreet Singh
Florian Gstrein
Eungnak Han
MARIE KRYSAK
Tayseer Mahdi
Xuanxuan CHEN
Brandon Jay Holybee

Assignees

INTEL CORPORATION

Dates

Publication Date: 20260512
Application Date: 20211027

Claims (10)

1 . An integrated circuit (IC) device, comprising: a first layer; and a second layer adjoining the first layer, the second layer comprising a plurality of lamellar structures, an individual one of the lamellar structures comprising: a first lamella comprising a first block of a triblock copolymer, wherein the first lamella is electrically insulating, a second lamella comprising a second block of the triblock copolymer, wherein the second lamella is electrically insulating, and a via between the first and second lamellae, the via including an electrically conductive material, wherein a first surface of the via contacts a surface of the first lamellae, a second surface of the via contacts a surface of the second lamellae, and the first surface of the via opposes the second surface of the via.
2 . The IC device according to claim 1 , wherein the first lamella and the second lamella comprise a same polymer.
3 . The IC device according to claim 2 , wherein the same polymer is includes at least one of polyethylene, polystyrene, polyvinylchloride, polytetrafluorethylene, polydimethylsiloxane, some polyesters, some polyurethanes, acrylics, epoxies, P(t-Butyl Acrylate), polyacrylic acid, polyacrylamide, maleic anhydride polymers, polyethylene, polypropylene, polyacrylonitrile, polybutadiene, polyvinyl acetate, polyacetic acid, polybutyl acrylate, polylactic acid, polycaprolactone, poly(ethylene glycol), and polyisoprene.
4 . The IC device according to claim 1 , wherein the first layer includes a plurality of first sections comprising a first material and a plurality of second sections comprising a second material that is different from the first material, and the via is in a portion of the second layer that adjoins one of the first sections of the first layer.
5 . The IC device according to claim 4 , wherein the first material is a dielectric material, and the second material is a metal or a metal compound.
6 . The IC device according to claim 4 , wherein the first material is a resist material, and the second material is a non-resist material.
7 . The IC device according to claim 1 , wherein an orientation of the lamellar structures is perpendicular to a surface of the first layer.
8 . The IC device according to claim 1 , wherein a ratio of a length of the lamellar structures along a direction perpendicular to the surface of the second layer to a length of the via along the direction is in a range from 0.3 to 2.0.
9 . The IC device according to claim 1 , wherein the plurality of lamellar structures are based on the triblock copolymer in a lamellar phase.
10 . The IC device according to claim 1 , wherein the via is a through via, a buried via, or a blind via.

Description

CROSS REFERENCE TO RELATED APPLICATION This application claims the benefit of U.S. Provisional Patent Application No. 63/128,264, filed Dec. 21, 2020, which is incorporated by reference its entirety. TECHNICAL FIELD This disclosure relates generally to semiconductor devices, and more specifically, to via opening of semiconductor devices. BACKGROUND For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize the performance of each device and each interconnect becomes increasingly significant. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. FIGS. 1A-1B illustrates a triblock copolymer in lamellar phase, in accordance with some embodiments. FIGS. 2-6 illustrate a process of forming via openings by using graphoepitaxy-based directed self-assembly (DSA) of a lamella triblock copolymer, in accordance with some embodiments. FIGS. 7A-7B illustrate a polymer nanocomposite, in accordance with some embodiments. FIGS. 8-11 illustrate a process of forming via openings by using the polymer nanocomposite, in accordance with some embodiments. FIGS. 12-15 illustrates a process of forming via openings by using chemoepitaxy, in accordance with some embodiments. FIGS. 16-20 illustrates a process of forming via openings based on a grating pattern of a grating layer, in accordance with some embodiments. FIGS. 21-24 illustrate a process of forming via openings by using mixed epitaxy, in accordance with some embodiments. FIG. 25 is a flowchart illustrating a process of using a lamellar triblock copolymer to rectify via openings, in accordance with various embodiments. FIG. 26 is a flowchart illustrating a process of using a polymer nanocomposite to rectify via openings, in accordance with various embodiments. FIG. 27 is a flowchart illustrating a process of using mixed epitaxy to rectify via openings, in accordance with various embodiments. FIGS. 28A-28B are top views of a wafer and dies that may include one or more via openings in accordance with any of the embodiments disclosed herein. FIG. 29 is a side, cross-sectional view of an example IC package that may include one or more IC devices having one or more via openings in accordance with any of the embodiments disclosed herein. FIG. 30 is a cross-sectional side view of an IC device assembly that may include components having one or more IC devices implementing one or more via openings in accordance with any of the embodiments disclosed herein. FIG. 31 is a block diagram of an example computing device that may include one or more integrated circuit (IC) devices with via openings rectified by using a lamellar triblock copolymer, a polymer nanocomposite, or mixed epitaxy, in accordance with various embodiments. DETAILED DESCRIPTION Overview Integrated circuits commonly include electrically conductive microelectronic structures, which are known in the arts as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Vias are typically formed by a lithographic process. Representatively, a photoresist layer may be spin coated over a dielectric layer, the photoresist layer may be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer may be developed to form an opening in the photoresist layer. Next, an opening for the via may be etched in the dielectric layer by using the opening in the photoresist layer as an etch mask. This opening is referred to as a via opening. An example via opening is a contact hole. Finally, the via opening may be filled with one or more metals or other conductive materials to form the via. The via may be a plating through via, blind via (e.g., a via connecting the outermost circuit of a printed circuit board (PCB) and the adjacent inner layer), buried via (e.g., a via connecting circuit layers of a PCB but not passing to the outer layer of the PCB), or other types of vias. In the past, the sizes and the spacing of vias has progressively decreased, and it is expected that in the future the sizes and the spacing of the vias will continue to progressively decrease, for at least some types of integrated circuits (e.g., a