US-12628630-B2 - Interconnect structure with reinforcing spacer and method for manufacturing the same

US12628630B2US 12628630 B2US12628630 B2US 12628630B2US-12628630-B2

Abstract

A method for manufacturing an interconnect structure includes: forming a first dielectric layer; forming a mask; patterning the first dielectric layer through the mask to form a trench, an inner surface of the trench having two first portions opposite to each other along an X direction, two second portions opposite to each other along a Y direction, and a bottom portion; forming a second dielectric layer over the mask and the patterned first dielectric layer, and along an inner surface of the trench; etching the second dielectric layer by directing an etchant in a predetermined direction such that a first part of the second dielectric layer on the two first portions and the bottom portion is removed, and a second part of the second dielectric layer on the second portions of the trench remains and is formed into two reinforcing spacers; and forming a trench-filling element.

Inventors

Wei-Hao Liao
HSIN-PING CHEN
Hsi-Wen Tien
Chih-Wei Lu
Hwei-Jay CHU
Yu-Teng Dai
Hsin-Chieh Yao
Yung-Hsu WU
Li-Ling SU
Chia-Wei Su

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260512
Application Date: 20231013

Claims (20)

1 . A method for manufacturing an interconnect structure, comprising: forming a first dielectric layer on a base structure; forming a mask on the first dielectric layer; patterning the first dielectric layer through the mask to form a trench in the patterned first dielectric layer, an inner surface of the trench having two first portions opposite to each other along an X direction, two second portions opposite to each other along a Y direction transverse to the X direction, and a bottom portion; forming two reinforcing spacers respectively on the two second portions of the trench such that the bottom portion and the two first portions of the trench are exposed from the two reinforcing spacers; and forming a trench-filling element in the trench to cover the two reinforcing spacers.
2 . The method according to claim 1 , wherein forming the two reinforcing spacers includes: forming a second dielectric layer along the inner surface of the trench; and removing a first part of the second dielectric layer located on the two first portions and the bottom portion, such that a second part of the second dielectric layer which remains on the two second portions serves as the two reinforcing spacers.
3 . The method according to claim 2 , wherein the second dielectric layer is conformally formed over the patterned first dielectric layer, the mask, and along the inner surface of the trench.
4 . The method according to claim 2 , wherein the first part of the second dielectric layer is removed using a directional etching process.
5 . The method according to claim 4 , wherein in the directional etching process, a ratio of a first etching rate of the first part of the second dielectric layer along the X direction to a second etching rate of the second part of the second dielectric layer along the Y direction is greater than 10.
6 . The method according to claim 1 , wherein: the base structure includes an etch stop layer on which the first dielectric layer is formed; and in patterning the first dielectric layer, a portion of the etch stop layer is exposed from the trench to serve as the bottom portion.
7 . The method according to claim 6 , further comprising, after forming the two reinforcing spacers, removing a portion of the etch stop layer exposed from the trench such that an underlying element of the base structure is exposed from trench, and in forming the trench-filling element, a bottom surface of the trench-filling element is connected to the underlying element.
8 . The method according to claim 1 , wherein forming the trench-filling element includes depositing an electrically conductive material layer over the two reinforcing spacers and the patterned first dielectric layer, and performing a planarization process to remove the mask, a portion of the patterned first dielectric layer, a portion of the two reinforcing spacers and a portion of the electrically conductive material layer.
9 . The method according to claim 1 , wherein the two reinforcing spacers are each formed with a thickness ranging from 10 Å to 200 Å.
10 . The method according to claim 1 , wherein the two reinforcing spacers have a dielectric constant lower than that of the patterned first dielectric layer.
11 . A method for manufacturing an interconnect structure, comprising: forming a first dielectric layer on a base structure; forming a mask on the first dielectric layer; patterning the first dielectric layer through the mask to form a trench in the patterned first dielectric layer, an inner surface of the trench having two first portions opposite to each other along an X direction, two second portions opposite to each other along a Y direction transverse to the X direction, and a bottom portion; forming a second dielectric layer over the mask and the patterned first dielectric layer, and along an inner surface of the trench; etching the second dielectric layer by directing an etchant in a predetermined direction such that a first part of the second dielectric layer on the two first portions and the bottom portion is removed, and a second part of the second dielectric layer on the two second portions of the trench remains and is formed into two reinforcing spacers; and forming a trench-filling element in the trench to cover the two reinforcing spacers.
12 . The method according to claim 11 , wherein the second dielectric layer is etched using an ion beam etching process.
13 . The method according to claim 12 , wherein the ion beam etching process is performed with a power ranging from 100 W to 3000 W.
14 . The method according to claim 12 , wherein the ion beam etching process is performed with a bias not greater than 20 kV.
15 . The method according to claim 11 , wherein, in etching the second dielectric layer, a ratio of an etching rate of the first part of the second dielectric layer to an etching rate of the mask is greater than 5.
16 . The method according to claim 11 , wherein: the base structure includes an etch stop layer on which the first dielectric layer is formed; and in patterning the first dielectric layer, a portion of the etch stop layer is exposed from the trench to serve as a bottom portion.
17 . The method according to claim 16 , further comprising, after etching the second dielectric layer, removing the portion of the etch stop layer exposed from the trench such that an underlying element of the base structure is exposed from the trench, and in forming the trench-filling element, a bottom surface of the trench-filling element is connected to the underlying element.
18 . The method according to claim 16 , wherein, in etching the second dielectric layer, a ratio of an etching rate of the first part of the second dielectric layer to an etching rate of the etch stop layer is greater than 7.
19 . An interconnect structure, comprising: a patterned first dielectric layer; conductive elements disposed in the patterned first dielectric layer and arranged in an array, each of the conductive elements having two first surfaces each confronting an adjacent one of the conductive elements in an X direction, two second surfaces each confronting an adjacent one of the conductive elements in a Y direction transverse to the X direction; and multiple pairs of reinforcing spacers, each pair of which are respectively formed on the two second surfaces of a respective one of the conductive elements, and each pair of which are formed between the patterned first dielectric layer and the respective one of the conductive elements such that the two first surfaces of each of the conductive elements are directly connected to the patterned first dielectric layer, the multiple pairs of the reinforcing spacers having a dielectric constant lower than that of the patterned first dielectric layer.
20 . The interconnect structure according to claim 19 , further comprising a patterned etch stop layer disposed on a bottom surface of the patterned first dielectric layer, the conductive elements each penetrating through the patterned first dielectric layer and the patterned etch stop layer.

Description

BACKGROUND In order to meet the demand of shrinkage of device size, metal lines at interconnect structures are designed to be close to each other, causing the interferences from RC delay due to parasitic resistance and capacitance to become greater, resulting in poor device performance. As such, development of interconnect structures with less RC delay is important. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a flow diagram illustrating a method for manufacturing an interconnect structure in accordance with some embodiments. FIGS. 2 to 21 are schematic views illustrating intermediate stages of the method for manufacturing the interconnect structure in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “on,” “above,” “top,” “bottom,” “bottommost,” “upper,” “uppermost.” “lower,” “lowermost,” “over,” “beneath,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. For the purposes of this specification and appended claims, unless otherwise indicated, all numbers expressing amounts, sizes, dimensions, proportions, shapes, formulations, parameters, percentages, quantities, characteristics, or other numerical values used in the specification and claims, are to be understood as being modified in all instances by the term “about” even if the term “about” is not explicitly recited with the values, amounts or ranges. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the following specification and appended claims are not and need not be exact, but may be approximations and/or larger or smaller than specified as desired, may encompass tolerances, conversion factors, rounding off, measurement error, and other factors known to those of skill in the art depending on the desired properties sought to be obtained by the presently disclosed subject matter. For example, the term “about,” when used with a value, can capture variations of, in some aspects ±10%, in some aspects +5%, in some aspects ±2.5%, in some aspects ±1%, in some aspects ±0.5%, and in some aspects ±0.1% from the specified amount, as such variations are appropriate to perform the disclosed methods or employ the disclosed compositions. The present disclosure is directed to an interconnect structure, and a method for manufacturing the same. The interconnect structure includes conductive elements, such as metal lines, that are formed in a patterned first dielectric layer and arranged in an array along an X direction and a Y direction. The X direction and the Y direction are transverse to each other. Each of the conductive elements has two first surfaces, each confronting an adjacent one of the conductive elements in the X direction, and two second surfaces, each confronting an adjacent one of the conductive elements in the Y direction. The interconnect structure also includes multiple pairs of reinforcing spacers. Each pair of the reinforcing spacers is respectively formed on the two second surfaces of a respective one of the conductive elements, and is formed between the patterned first dielectric layer and the respective one of the conductive elements, such that the two first surfaces of each of the conductive