US-12628631-B2 - Device with backside power rail and method

Abstract

A device includes a stack of semiconductor nanostructures, a gate structure wrapping around the semiconductor nanostructures, a source/drain region abutting the gate structure and the stack, a contact structure on the source/drain region, a backside dielectric layer under the stack, and a via structure extending from the contact structure to a top surface of the backside dielectric layer.

Inventors

• Yun Ju FAN
• Huan-Chieh Su
• Chun-Yuan Chen
• Cheng-Chi Chuang
• Chih-Hao Wang

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date

20260512

Application Date

20220805

Claims (20)

1. 1 . A device, comprising: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures; a source/drain region abutting the gate structure and the stack; a contact structure disposed on a front side of the source/drain region over the source/drain region; a backside dielectric layer disposed at a backside of the device under the stack, the backside being opposite the frontside at which the contact structure is disposed; and a via structure extending from the contact structure to a top surface of the backside dielectric layer.
2. 2 . The device of claim 1 , wherein a first portion of an upper surface of the via structure is in contact with the contact structure, and a second portion of the upper surface is in contact with an isolation layer.
3. 3 . The device of claim 1 , wherein the entirety of an upper surface of the via structure is in contact with the contact structure.
4. 4 . The device of claim 1 , wherein a portion of a sidewall of the via structure is in contact with the contact structure.
5. 5 . The device of claim 4 , wherein the via structure is laterally separated from the source/drain region by an isolation layer.
6. 6 . The device of claim 1 , further comprising a semiconductor fin between the stack and the backside dielectric layer.
7. 7 . The device of claim 1 , wherein the via structure has width that increases with proximity to the backside dielectric layer.
8. 8 . A method, comprising: forming a vertical stack of nanostructure channels over a substrate; forming a source/drain region abutting the nanostructure channels; forming a gate structure wrapping around the nanostructure channels; forming a via structure adjacent the source/drain region and laterally isolated from the source/drain region; forming a contact structure in contact with the via structure and the source/drain region; and forming a backside interconnect structure in contact with the via structure.
9. 9 . The method of claim 8 , wherein the forming a via structure includes: forming a first opening that removes a portion of the gate structure; forming a dielectric plug in the first opening; forming a second opening exposing the substrate by removing at least a portion of the dielectric plug; and forming the via structure in the second opening.
10. 10 . The method of claim 9 , wherein the forming a dielectric plug includes: forming an isolation layer in the first opening; and forming a dielectric plug layer on the isolation layer.
11. 11 . The method of claim 10 , wherein a top portion of the isolation layer is recessed when forming the second opening.
12. 12 . The method of claim 9 , wherein the forming a via structure includes: forming an intermediate device structure by forming a dielectric layer in the second opening; exposing the substrate by flipping the intermediate device structure; exposing a bottom side of the dielectric layer by removing the substrate; opening the second opening by removing the dielectric layer, the second opening exposing the contact structure; and forming the via structure by depositing material of the via structure in the second opening while the intermediate device structure is flipped.
13. 13 . The method of claim 8 , further comprising forming a backside power line in electrical contact with the via structure.
14. 14 . A method, comprising: forming a vertical stack of nanostructure channels over a substrate; forming a source/drain region abutting the nanostructure channels; forming a gate structure wrapping around the nanostructure channels; forming a gate isolation structure that isolates portions of the gate structure from each other; forming a contact structure having an underside in contact with the source/drain region and the gate isolation structure; exposing the gate isolation structure by removing the substrate; forming an opening in the gate isolation structure, the opening exposing the underside of the contact structure; and forming a via structure in the opening, the via structure being in contact with the contact structure.
15. 15 . The method of claim 14 , further comprising: forming a backside dielectric layer in contact with the via structure; exposing the via structure by forming a second opening in the backside dielectric layer; and forming a backside conductive feature in the second opening.
16. 16 . The method of claim 15 , further comprising: forming a power line in electrical connection with the backside conductive feature.
17. 17 . The method of claim 16 , further comprising: forming a second source/drain region abutting the nanostructure channels opposite the source/drain region; and forming a signal line electrically connected to the second source/drain region, the signal line being on a front side of the second source/drain region and vertically separated from the second source/drain region by a frontside dielectric layer.
18. 18 . The method of claim 14 , wherein removing the substrate removes a semiconductor fin underlying the vertical stack of nanostructure channels.
19. 19 . The method of claim 14 , wherein the forming an opening in the gate isolation structure includes removing a portion of a dielectric plug layer of the gate isolation structure under the contact structure.
20. 20 . The method of claim 19 , wherein the forming an opening in the gate isolation structure further includes removing a portion of an isolation layer of the gate isolation structure, the portion being in contact with the contact structure.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application claims the benefit of priority to U.S. Provisional Application Ser. No. 63/327,257, entitled “SEMICONDUCTOR DEVICES AND METHODS HAVING BACKSIDE POWER DELIVERY WITH FRONTSIDE POWER VIA,” filed on Apr. 4, 2022, which application is incorporated by reference herein in its entirety. BACKGROUND The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A, 1B, IC, 1D, 1E, IF, 1G and 1H are diagrammatic plan, perspective and cross-sectional side views of a portion of an IC device according to embodiments of the present disclosure. FIGS. 2A, 2B, 3A, 3B, 4A, 4B, 4C, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 8C, 9A, 9B, 9C, 10A, 10B, 10C, and 10D are views of various embodiments of an IC device of at various stages of fabrication according to various aspects of the present disclosure. FIGS. 11A, 11B, 11C, 11D, 11E, 11F, 11G, 11H, 11I, and 11J are views of various embodiments of an IC device at various stages of forming a frontside via for backside power delivery in accordance with various embodiments. FIGS. 12A, 12B, 12C, 12D, 12E, 12F, 12G, 12H, and 12I are views of various embodiments of an IC device at various stages of forming a frontside via for backside power delivery in accordance with various embodiments. FIGS. 13A, 13B, 13C, 13D, 13E, 13F, and 13G are views of various embodiments of an IC device at various stages of forming a frontside via for backside power delivery in accordance with various embodiments. FIGS. 14, 15, and 16 are flowcharts illustrating methods of fabricating a semiconductor device according to various aspects of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. The present disclosure is generally related to semiconductor devices, and more particularly to field-effect transistors (FETs), such as planar FETs, three-dimensional fin-line FETs (FinFETs), or nanostructure devices. Examples of nanostructure devices include gate-all-around (GAA) devices, nanosheet FETs (NSFETs), nanowire FETs (NWFETs), and the like. In advanced technology nodes, with scaling down of integrated circuit (IC) devices, routing both signal wires and power wires (or rails) at the frontside of the substrate is increasingly challenging. When scaling down, space for interconnects decreases, increasing difficulty of power rail design. For example, power rail