US-12628632-B2 - Semiconductor package and manufacturing method thereof

US12628632B2US 12628632 B2US12628632 B2US 12628632B2US-12628632-B2

Abstract

A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.

Inventors

Jen-Chun Liao
Sung-Yueh Wu
Chien-Ling Hwang
Ching-Hua Hsieh

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260512
Application Date: 20240612

Claims (20)

1 . A substrate structure, for supporting and routing at least one semiconductor die, and comprising: a heat dissipating substrate; a through substrate via, penetrating through the heat dissipating substrate, and having a first portion extending into the heat dissipating substrate from a first side of the heat dissipating substrate and a second portion connected to the first portion and extending to a second side of the heat dissipating substrate, wherein a second sidewall of the second portion is formed with a second slope greater a first slope of a first sidewall of the first portion; a first conductive pattern, disposed along the first side of the heat dissipating substrate and connected to the first portion of the through substrate via, wherein the first conductive pattern comprises a patterned seed layer laterally extending along the first side of the heat dissipating substrate away from the through substrate via and a patterned conductive layer covering the patterned seed layer and the through substrate via; and a second conductive pattern, disposed along the second side of the heat dissipating substrate and an end of the second portion of the through substrate via, and connected to the second portion of the through substrate via.
2 . The substrate structure according to claim 1 , wherein the heat dissipating substrate is formed of a ceramic material.
3 . The substrate structure according to claim 1 , wherein the through substrate via tapers toward the second side of the heat dissipating substrate from the first side of the heat dissipating substrate.
4 . The substrate structure according to claim 1 , wherein a patterned seed layer of the second conductive pattern lines along the second side of the heat dissipating substrate and the end of the second portion of the through substrate via, and a patterned conductive layer of the second conductive pattern covers the patterned seed layer of the second conductive pattern.
5 . The substrate structure according to claim 1 , wherein a thickness of the first portion of the through substrate via is shorter than a thickness of the second portion of the through substrate via.
6 . The substrate structure according to claim 1 , wherein a thickness of the first portion of the through substrate via is substantially equal to or greater than a thickness of the second portion of the through substrate via.
7 . The substrate structure according to claim 1 , wherein a patterned seed layer of the through substrate via lines along the first sidewall and the second sidewall, and a patterned conductive layer of the through substrate via is laterally surrounded by the patterned seed layer of the through substrate via.
8 . The substrate structure according to claim 7 , wherein the second conductive pattern comprises a patterned seed layer and an overlying patterned conductive layer, and the patterned seed layer and the patterned conductive layer of the through substrate via extend to reach the patterned seed layer of the second conductive pattern.
9 . The substrate structure according to claim 1 , wherein the through substrate via comprises a cured conductive paste.
10 . The substrate structure according to claim 9 , wherein the cured conductive paste is in direct contact with the heat dissipating substrate without a seed layer in between.
11 . The substrate structure according to claim 1 , wherein the patterned seed layer of the first conductive pattern is connected to a patterned seed layer of the through substrate via, and the patterned conductive layer of the first conductive pattern is connected to a patterned conductive layer of the through substrate via.
12 . The substrate structure according to claim 1 , wherein the through substrate via comprises an obtuse angle between the first sidewall and the second sidewall.
13 . The substrate structure according to claim 1 , wherein an obtuse angle is between the second sidewall of the through substrate via and the second conductive pattern.
14 . A substrate structure, for supporting and routing at least one semiconductor die, and comprising: a substrate comprising a first surface and a second surface opposite to the first surface; a through substrate via (TSV) extending through the substrate, the TSV comprising: a first portion extending into the substrate from the first surface and comprising a first sidewall; and a second portion connected to the first portion and extending to the second surface, the second portion comprising a second sidewall, wherein a first angle by which the first sidewall tilts from a thickness direction of the substrate is greater than a second angle by which the second sidewall tilts from the thickness direction; and a first conductive pattern connected to the TSV, the first conductive pattern comprising a first seed layer and a first conductive layer overlying the first seed layer, wherein the at least one semiconductor die is routed through the substrate structure via the first conductive pattern and the TSV.
15 . The substrate structure according to claim 14 , wherein the TSV comprises an included angle between the first sidewall and the second sidewall, and the included angle is an obtuse angle.
16 . The substrate structure according to claim 14 , wherein the substrate is made of a heat-dissipating material.
17 . The substrate structure according to claim 14 , wherein a thickness of first portion of the TSV is less than a thickness of the second portion of the TSV.
18 . The substrate structure according to claim 14 , wherein the TSV further comprises: a second seed layer connected to the first seed layer of the first conductive pattern; and a second conductive layer overlying the second seed layer and connected to the first conductive layer of the first conductive pattern, wherein the first seed layer and the second seed layer separates the first conductive layer and the patterned conductive layer from the substrate.
19 . The substrate structure according to claim 14 , wherein the TSV is made of a conductive paste.
20 . A substrate structure, for supporting and routing at least one semiconductor die, and comprising: a substrate comprising a first surface and a second surface opposite to the first surface; a through substrate via (TSV) passing through the substrate, the TSV comprising: a first portion extending into the substrate from the first surface, the first portion comprising a first cross-sectional profile and a first maximum lateral dimension; and a second portion connected to the first portion and extending to the second surface, the second portion comprising a second cross-sectional profile different from the first cross-sectional profile and a second maximum lateral dimension less than the first maximum lateral dimension; and a conductive pattern disposed on the first surface of the substrate and connected to the TSV, the conductive pattern comprising a seed layer and a conductive layer overlying the seed layer, wherein the at least one semiconductor die is routed through the substrate structure via the conductive pattern and the TSV.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation application of and claims the priority benefit of a prior application Ser. No. 18/361,917, filed on Jul. 31, 2023, now allowed. The prior application Ser. No. 18/361,917 is a continuation application of and claims the priority benefit of a prior application Ser. No. 17/185,966, filed on Feb. 26, 2021, U.S. Pat. No. 11,764,127B2. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. As electronic products are continuously miniaturized, heat dissipation of semiconductor devices has become an important issue for packaging technology. Moreover, in the packaging of semiconductor devices, through via connections may be used to provide electrical connections between the vertically arranged integrated circuit components. The formation of these through vias has impacts on data transmission speed and reliability of the semiconductor devices. There is a continuous need for more reliable semiconductor devices having improved electrical performance. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A-1E are schematic cross-sectional views of various stages of manufacturing a substrate structure in accordance with some embodiments. FIGS. 2A-2C are schematic cross-sectional views of various stages of manufacturing a substrate structure in accordance with some embodiments. FIGS. 3A-3C are schematic cross-sectional views of various stages of manufacturing a semiconductor package including a substrate structure in accordance with some embodiments. FIG. 4 is a schematic cross-sectional view of a semiconductor package including a substrate structure in accordance with some embodiments. FIG. 5 is a schematic cross-sectional view of a package structure including a semiconductor package in accordance with some embodiments. FIG. 6 is a schematic cross-sectional view of a semiconductor package including a substrate structure in accordance with some embodiments. FIG. 7 is a schematic cross-sectional view of a semiconductor structure including a substrate structure in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yie