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US-12628633-B2 - Semiconductor device including spacer via structure and method of manufacturing the same

US12628633B2US 12628633 B2US12628633 B2US 12628633B2US-12628633-B2

Abstract

A connection structure for an integrated circuit includes: a 1 st layer including a 1 st metal line; a 2 nd layer, above the 1 st layer, including a 1 st via; and a 3 rd layer, above the 2 nd layer, including a 2 nd metal line connected to the 1 st metal line through the 1 st via, wherein the 1 st via comprises a spacer structure at a side of an upper portion of the 1 st via, the spacer structure comprising an insulation material.

Inventors

  • Janggeun LEE
  • Jaemyung CHOI
  • Kang-ill Seo

Assignees

  • SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date
20260512
Application Date
20220615

Claims (8)

  1. 1 . A method of manufacturing a connection structure for an integrated circuit, the method comprising: forming a 1 st layer comprising a 1 st metal line; forming a 2 nd layer, above the 1 st layer, comprising an initial via structure vertically connected to the 1 st metal line; removing an upper portion of the initial via structure from the 2 nd layer to form a hole exposing a top surface of a lower portion of the initial via structure; forming a spacer layer along a side surface of the hole, wherein the spacer layer has a horizontal thickness that is uniform along the side surface of the hole; filling the hole with a via material to be combined with the lower portion of the initial via structure to form a 1 st via comprising metal in the 2 nd layer; and forming a 3 rd layer comprising a 2 nd metal line above the 2 nd layer such that the 1 st via is vertically connected to the 2 nd metal line through metal-to-metal connection.
  2. 2 . The method of claim 1 , wherein the forming the 3 rd layer comprises: forming a 3 rd metal line adjacent to the 2 nd metal line in the 3 rd layer; isolating the 2 nd metal line from the 3 rd metal line through an interlayer dielectric (ILD) layer; and isolating the 1 st via from the 3 rd metal line through the spacer layer and the ILD layer.
  3. 3 . The method of claim 2 , further comprising: forming a 4th layer, above the 3 rd layer, comprising a 2 nd via connected to the 3 rd metal line; and forming a 5th layer, above the 4th layer, comprising a 4th metal line connected to the 2 nd via.
  4. 4 . The method of claim 1 , wherein the 1 st via is directly connected to the 2 nd metal line.
  5. 5 . The method of claim 2 , wherein a horizontal distance between an upper-right or upper-left edge of the 1 st via contacting the spacer layer and the 3rd metal line is greater than a horizontal distance between the 2 nd metal line and the 3 rd metal line.
  6. 6 . The method of claim 2 , wherein a horizontal distance between an upper-right or upper-left edge of the spacer layer, not contacting the 1 st via, and the 3 rd metal line is smaller than a horizontal distance between the 2 nd metal line and the 3 rd metal line.
  7. 7 . A method of manufacturing a connection structure for an integrated circuit, the method comprising: forming a 1 st layer comprising a 1 st metal line; forming a 2 nd layer, above the 1 st layer, comprising an initial via structure vertically connected to the 1 st metal line; removing an upper portion of the initial via structure from the 2 nd layer to form a hole exposing a top surface of a lower portion of the initial via structure; forming a spacer layer along a side surface of the hole, wherein the spacer layer has a horizontal thickness that is uniform along the side surface of the hole; filling the hole with a via material to be combined with the lower portion of the initial via structure to form a 1 st via comprising metal in the 2 nd layer, wherein a 3 rd layer is formed to further comprise a 3 rd metal line such that the 3rd metal line is isolated from the 1 st via, and comprises a protrusion in a form of via, wherein the 3 rd metal line comprises a metal line and the protrusion as a top via, and wherein the metal line and the protrusion is a single continuous structure without a connection surface therebetween.
  8. 8 . The method of claim 7 , wherein the 3 rd metal line has a height greater than the 2 nd metal line by a height of the protrusion.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority from U.S. Provisional Application No. 63/332,916 filed on Apr. 20, 2022 in the U.S. Patent and Trademark Office, the disclosure of which is incorporated herein in its entirety by reference. BACKGROUND 1. Field Apparatuses and methods consistent with example embodiments of the disclosure relate to a connection structure for an integrated circuit, and more particularly to a connection structure including a via structure to which a spacer is attached in a semiconductor device. 2. Description of the Related Art FIG. 1 illustrates a cross-sectional view of a back-end-of-line (BEOL) structure including a plurality of metal lines and vias formed in a plurality of layers. A BEOL structure 100 shown in FIG. 1 may be a part of or connected to an integrated circuit (not shown) such as a logic circuit, a memory flip-flop or a latch circuit formed of at least one semiconductor device to receive and output signals for the integrated circuit. Hereinafter, the “via” refers to a via structure or a via plug which is formed or filled in a via hole to connect two or more metal lines formed at vertically different stacks or layers. Also, the “metal line” refers to a metal pattern or a metal structure which may be connected to a circuit element such as a middle-of-line (MOL) element or a front-end-of-line (FEOL) element in a semiconductor device. For example, the metal line may be a power line connected to a voltage source (Vdd or Vss) to receive a positive voltage or a negative voltage supplied to a semiconductor device connected to the BEOL structure 100. As another example, the metal line itself may be an MOL element such as a gate contact structure connected to a gate electrode of a transistor or a source/drain contact structure connected to a source/drain region of the transistor included in the semiconductor device. Thus, the BEOL structure 100 may be actually a combination of a BEOL structure and an MOL structure. The BEOL structure 100 shown in FIG. 1 includes five layers L1 to L5 stacked in a D3 direction, and a plurality of metal lines and a plurality of vias are respectively formed in the layers L1 to L5. Referring to FIG. 1, a lower metal layer L1 includes a lower metal line M1 that may be connected to a transistor structure TR formed therebelow. The transistor structure TR may include one or more MOL and FEOL elements of a transistor such as a fin field-effect transistor (FinFET) or a nanosheet transistor which is also referred to as multi-bridge channel field-effect transistor (MBCFET). FIG. 1 also shows that an upper metal layer L5 includes an upper metal line M3 which may receive a power signal or may be used for internal signal routing of the semiconductor device. For example, the lower metal line M1 or the upper metal line M3 may be used as a power line, a gate contact structure, or a source/drain region contact structure of the transistor structure TR, not being limited thereto. The lower metal line M1 and the upper metal line M3 may each be formed in respective trenches (not shown) extended in a D1 direction. FIG. 1 further shows that a 1st via layer L2, a 2nd metal layer L3 and a 2nd via layer L4 are sequentially stacked in the D3 direction between the lower metal layer L1 and the upper metal layer L5. The 2nd metal layer L3 includes a plurality 2nd metal lines M21 to M24 which are formed in respective trenches T1 to T4 extending in a D2 direction perpendicular to the D1 direction. The 2nd metal lines M21 to M24 may also be used to receive a power signal or may be used for internal signal routing of the semiconductor device. The 2nd metal lines M21 and M23 are vertically connected to the lower metal line M1 through 1st vias V11 and V12, respectively, formed in respective 1st via holes VH11 and VH12 provided in the 1st via layer L2. Each of the 1st via holes VH11 and VH12 has an aspect ratio of width w1 to height h1. The other 2nd metal lines M22 and M24 are vertically connected to the upper metal line M3 through 2nd vias V21 and V22, respectively, formed in respective 2nd via holes VH21 and VH22 in the 2nd via layer L4. The plurality of metal lines and vias formed in the layers L1 to L5 may be formed of the same or different metals or metal compounds including at least one of copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), etc. Further, the BEOL structure 100 includes 1st to 3rd interlayer dielectric (ILD) structures ILD1 to ILD3 respectively formed in the 2nd to 4th layers L2 to L4 to respectively isolate or insulate the 1st vias V11 and V12, the 2nd metal lines M21 to M24, and the 2nd vias V21 and V22 from one another or from horizontally neighboring circuit elements (not shown). The 1st to 3rd ILD structures ILD1 to ILD3 may be formed of at least one of low-k materials such as silicon, carbon, silicon oxide and silicon nitride. The low-k material may