US-12628634-B2 - Via resistance reduction

Abstract

Interconnect designs with reduced via resistance are provided. In one aspect, an interconnect structure includes: at least a first metal line and a second metal line; and a conductive via in between the first metal line and the second metal line, wherein the conductive via has elongated dimensions along a major axis of the first metal line and along a major axis of the second metal line. Dielectric caps can be present on the first metal lines, and below and above the second metal lines. A method of forming the present interconnect structure is also provided.

Inventors

• Ruilong Xie
• Nicholas Anthony Lanzillo
• Brent A Anderson
• Reinaldo Vega
• Albert M. Chu
• Lawrence A. Clevenger

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260512

Application Date

20220803

Claims (11)

1. 1 . An interconnect structure, comprising: at least a first metal line and a second metal line; and a conductive via in between the first metal line and the second metal line, wherein the conductive via has a first elongated dimension along a major axis of the first metal line and the conductive via has a second elongated dimension along a major axis of the second metal line, wherein the conductive via has a vertical shaft that connects the first elongated dimension and the second elongated dimension, wherein the major axis of the first metal line and the major axis of the second metal line are perpendicular to each other, wherein the first elongated dimension extends outwards from the vertical shaft in two directions along the first major axis of the first metal line to form a T-shape, wherein the second elongated dimension extends outwards from the vertical shaft in two directions along the second major axis of the second metal line to form an inverted T-shape.
2. 2 . The interconnect structure of claim 1 , wherein the conductive via has substantially a same dimension as the first metal line along a minor axis of the first metal line, and wherein the conductive via has substantially a same dimension as the second metal line along a minor axis of the second metal line.
3. 3 . The interconnect structure of claim 1 , wherein the first metal line is oriented orthogonal to the second metal line.
4. 4 . The interconnect structure of claim 1 , wherein the first metal line is present below the conductive via and the second metal line is present above the conductive via, and wherein the interconnect structure further comprises: dielectric caps both below and above the second metal line.
5. 5 . The interconnect structure of claim 4 , wherein the dielectric caps each comprises a material selected from the group consisting of: silicon nitride (SiN), silicon carbide (SiC), silicon dioxide (SiO2), silicon oxycarbide (SiCO), aluminum nitride (AlNx), aluminum oxide (AlOx) and combinations thereof.
6. 6 . An interconnect structure, comprising: first metal lines; first dielectric caps on the first metal lines; a conductive via disposed directly on a given one of the first metal lines; second metal lines over the first metal lines with a given one of the second metal lines disposed directly on the conductive via, wherein the conductive via has a first elongated dimension along a major axis of the given first metal line and the conductive via has a second elongated dimension along a major axis of the given second metal line, wherein the conductive via has a vertical shaft that connects the first elongated dimension and the second elongated dimension, wherein the major axis of the first metal line and the major axis of the second metal line are perpendicular to each other, wherein the first elongated dimension extends outwards from the vertical shaft in two directions along the first major axis of the first metal line to form a T-shape, wherein the second elongated dimension extends outwards from the vertical shaft in two directions along the second major axis of the second metal line to form an inverted T-shape; second dielectric caps present below the second metal lines; and third dielectric caps present above the second metal lines.
7. 7 . The interconnect structure of claim 6 , wherein the conductive via has substantially a same dimension as the given first metal line along a minor axis of the given first metal line, and wherein the conductive via has substantially a same dimension as the given second metal line along a minor axis of the given second metal line.
8. 8 . The interconnect structure of claim 6 , wherein the first metal lines are oriented orthogonal to the second metal lines.
9. 9 . The interconnect structure of claim 6 , wherein the first metal lines and the first dielectric caps are embedded in a first interlayer dielectric.
10. 10 . The interconnect structure of claim 9 , wherein the second metal lines, the second dielectric caps and the third dielectric caps are embedded in a second interlayer dielectric.
11. 11 . The interconnect structure of claim 6 , wherein the first dielectric caps, the second dielectric caps and the third dielectric caps each comprises a material selected from the group consisting of: SiN, SiC, SiO2, SiCO, AlNx, AlOx and combinations thereof.

Description

FIELD OF THE INVENTION The present invention relates to interconnect structures, and more particularly, to interconnect designs with reduced via resistance, and techniques for fabrication thereof by locally increasing the via size. BACKGROUND OF THE INVENTION In a semiconductor integrated circuit back end of line (BEOL) production flow, individual devices such as transistors, diodes, capacitors, resistors, etc. get interconnected through a series of metal layers. For instance, conductive structures like vias and metal lines can be employed to connect a device to one or more other devices, with the metal lines making lateral connections and the vias making vertical connections amongst different metallization levels. However, at scaled dimensions, reducing the BEOL pitch means that the via size gets increasingly smaller, thereby creating a resistance bottle neck for advanced designs. Namely, there is a point beyond which conventional interconnects cannot be scaled without incurring an unacceptable tradeoff in device performance. Therefore, scalable interconnect designs that avoid this via resistance bottle neck would be desirable. SUMMARY OF THE INVENTION The present invention provides improved interconnect designs with reduced via resistance, and techniques for fabrication thereof by locally increasing the via size. In one aspect of the invention, an interconnect structure is provided. The interconnect structure includes: at least a first metal line and a second metal line; and a conductive via in between the first metal line and the second metal line, wherein the conductive via has elongated dimensions along a major axis of the first metal line and along a major axis of the second metal line. In another aspect of the invention, another interconnect structure is provided. The interconnect structure includes: first metal lines; first dielectric caps on the first metal lines; a conductive via disposed directly on a given one of the first metal lines; second metal lines over the first metal lines with a given one of the second metal lines disposed directly on the conductive via, wherein the conductive via has elongated dimensions along a major axis of the given first metal line and along a major axis of the given second metal line; second dielectric caps present below the second metal lines; and third dielectric caps present above the second metal lines. In yet another aspect of the invention, a method of forming an interconnect structure is provided. The method includes: forming first metal lines and first dielectric caps on the first metal lines embedded in a first interlayer dielectric; depositing a second interlayer dielectric onto the first interlayer dielectric over the first metal lines and the first dielectric caps; forming trenches in the second interlayer dielectric; forming second dielectric caps at bottoms of the trenches; patterning a via through a given one of the second dielectric caps, the second interlayer dielectric, and a given one of the first dielectric caps over a given one of the first metal lines; laterally recessing the given first dielectric cap and the given second dielectric cap through the via to locally elongate the dimensions of the via; and forming a conductive via in the via and second metal lines in the trenches with a given one of the second metal lines over the conductive via, wherein the conductive via has elongated dimensions along a major axis of the given first metal line and along a major axis of the given second metal line. A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of the present interconnect structure where the conductive via size has been increased locally according to an embodiment of the present invention; FIG. 2 is a top-down diagram illustrating an orientation of the X-X′ and Y-Y′ cross-sectional views shown in the figures according to an embodiment of the present invention; FIG. 3A is an X-X′ cross-sectional view illustrating first metal lines (Mx-1) having been formed on a substrate, and FIG. 3B is a Y-Y′ cross-sectional view illustrating the first metal lines (Mx-1), which are embedded in a (first) interlayer dielectric, having been formed on the substrate according to an embodiment of the present invention; FIG. 4A is an X-X′ cross-sectional view illustrating (first) dielectric caps having been formed on each of the first metal lines, and FIG. 4B is a Y-Y′ cross-sectional view illustrating the first dielectric caps having been formed on each of the first metal lines according to an embodiment of the present invention; FIG. 5A is an X-X′ cross-sectional view illustrating a (second) interlayer dielectric having been deposited onto the first interlayer dielectric over the first metal lines and the first dielectric caps, and FIG. 5B is a Y