US-12628635-B2 - Selective deposition of liner and barrier films for resistance reduction of semiconductor devices

US12628635B2US 12628635 B2US12628635 B2US 12628635B2US-12628635-B2

Abstract

A semiconductor device includes a field-effect transistor (FET) having a source/drain (S/D) structure and an interconnect structure in contact with the S/D structure. The interconnect structure has a barrier film at a surface of the interconnect structure separating the interconnect structure from materials surrounding the interconnect structure. A first portion of the barrier film covers a first interface between the interconnect structure and the S/D structure. A second portion of the barrier film covers a second interface between the interconnect structure and dielectric materials adjacent to the interconnect structure. The first portion of the barrier film is thicker than the second portion of the barrier film.

Inventors

Jeffrey Smith
Hiroaki Niimi
Kandabara Tapily
Daniel Chanemougame
Lars Liebmann

Assignees

TOKYO ELECTRON LIMITED

Dates

Publication Date: 20260512
Application Date: 20220808

Claims (8)

1 . A semiconductor device, comprising: a field-effect transistor (FET) having a source/drain (S/D) structure that includes a silicide layer surrounding an entire surface of the S/D structure; and an interconnect structure in contact with the S/D structure, wherein the interconnect structure has a barrier film at a surface of the interconnect structure separating the interconnect structure from materials surrounding the interconnect structure, a first portion of the barrier film covers a first interface between the interconnect structure and a portion of the silicide layer of the S/D structure, a second portion of the barrier film covers a second interface between the interconnect structure and dielectric materials adjacent to the interconnect structure, the first portion of the barrier film is thicker than the second portion of the barrier film, and the first portion of the barrier film does not contain a material of the second portion of the barrier film.
2 . The semiconductor device of claim 1 , wherein the second portion of the barrier film covers a surface of a via structure of the interconnect structure.
3 . The semiconductor device of claim 2 , wherein the via structure connects the interconnect structure to a power rail.
4 . A semiconductor device, comprising: a first source/drain (S/D) structure of a first field-effect transistor (FET); and a first interconnect structure in contact with the first S/D structure, wherein the first S/D structure includes a silicide layer in a first portion of a surface of the first S/D structure, the silicide layer in contact with an interface between the first S/D structure and the first interconnect structure, and the first S/D structure includes a contact etch stop layer (CESL) in direct contact with a second portion of the surface of the first S/D structure, the CESL not existing in the first portion of the surface of the first S/D structure, wherein the silicide layer and the CESL cover the entire surface of the first S/D structure.
5 . The semiconductor device of claim 4 , further comprising: a first embedded power rail, wherein the first interconnect structure includes a first via interconnect structure connecting the first interconnect structure to the first embedded power rail.
6 . The semiconductor device of claim 5 , further comprising: a second S/D structure of a second FET formed on top of the first FET; and a second interconnect structure in contact with the second S/D structure, wherein the second interconnect structure includes a second via interconnect structure connecting the second interconnect structure to a second embedded power rail, and the second via interconnect structure is in contact with the CESL of the first S/D structure.
7 . The semiconductor device of claim 4 , wherein the silicide layer includes a layer of titanium (Ti), and the CESL includes a layer of silicon nitride (SIN).
8 . The semiconductor device of claim 4 , wherein the semiconductor device is a complementary FET (CFET) device.

Description

TECHNICAL FIELD The present disclosure describes embodiments generally related to semiconductor devices and manufacturing processes. BACKGROUND The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. Transistors, such as field-effect transistors (FETs), are the basic elements of microelectronics and integrated circuits. There has been a continuous drive to scale down or shrink transistors and other semiconductor devices to increase density and improve processing performance. Historically, transistors have been created in one plane, with wiring/metallization formed above the active device plane. Recently, three-dimensional (3D) fabrication has been developed to utilize the vertical axis to improve transistor density. For example, a new device architecture known as complementary FET (CFET) can include transistors that are stacked one over the other. SUMMARY Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a field-effect transistor (FET) having a source/drain (S/D) structure and an interconnect structure in contact with the S/D structure. The interconnect structure has a barrier film at a surface of the interconnect structure separating the interconnect structure from materials surrounding the interconnect structure. A first portion of the barrier film covers a first interface between the interconnect structure and the S/D structure. A second portion of the barrier film covers a second interface between the interconnect structure and dielectric materials adjacent to the interconnect structure. The first portion of the barrier film is thicker than the second portion of the barrier film. In an embodiment, the second portion of the barrier film covers a surface of a via structure of the interconnect structure. The via structure can connect the interconnect structure to a power rail. In some examples, the first portion of the barrier and the second portion of the barrier film are formed using the same material. Aspects of the disclosure further provide a method of manufacturing a semiconductor device. The method can include forming a trench structure through dielectric materials to expose a S/D structure of a FET, selectively forming a first barrier film on a surface of a silicide layer of the exposed S/D structure to seal the exposed S/ID structure, conformally forming a second barrier film on an inner surface of the trench structure, the second barrier film overlapping the first barrier film, and filling a conductive material into the trench structure to form an interconnect structure for the S/ID structure. In an example, the selectively forming the first barrier film can include performing a selective deposition process in which a deposition of the first barrier film on the surface of the silicide layer of the exposed S/D structure is selective to the dielectric materials surrounding the trench structure. In an example, the first barrier film is thicker than the second barrier film. In an example, the trench structure includes a via structure at a bottom of the trench structure, and an inner surface of the via structure is covered by the second barrier film but not by the first barrier film. In an example, the via structure reaches an embedded power rail. In an example, the silicide layer of the exposed S/D structure includes a layer of titanium, titanium silicide, nickel, nickel silicide, platinum, platinum silicide, ruthenium, or ruthenium silicide. The dielectric materials surrounding the trench structure include one of silicon oxide, silicon nitride, or silicon carbon nitride (SiCN). The semiconductor device is a complementary field-effect transistor (CFET). Aspects of the disclosure can further provide another semiconductor device. The semiconductor device can include a first S/D structure of a first FET and a first interconnect structure in contact with the first S/D structure. The first S/D structure includes a silicide layer in a first portion of a surface of the first S/D structure. The silicide layer can be in contact with an interface between the first S/D structure and the first interconnect structure. The first S/D structure includes a contact etch stop layer (CESL) in a second portion of the surface of the first S/D structure. The CESL does not exist in the first portion of the surface of the first S/D structure. In an example, the semiconductor device can further include a first embedded power rail. The first interconnect structure includes a first via interconnect structure connecting the first interconnect structure to the first embedded power rail. In an example, the semiconductor device can furthe