US-12628636-B2 - Semiconductor structure with top via having extended bottom contact

US12628636B2US 12628636 B2US12628636 B2US 12628636B2US-12628636-B2

Abstract

A semiconductor structure that includes a metal level, a via located directly on top of a first portion of the metal level, wherein the via is tapered such that a smaller critical dimension is located at a top portion of the via and a larger critical dimension is located at a bottom portion of the via, and the bottom portion of the via is located adjacent the metal level, a dielectric cap located on top of a second portion of the metal level on which the via is not located directly thereon, and a next metal level that is located directly on the top portion of the via.

Inventors

Manasa Medikonda
Tao Li
Ruilong Xie
Chih-Chao Yang

Assignees

INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date: 20260512
Application Date: 20230504

Claims (14)

1 . A semiconductor structure, comprising: a metal level; a via located directly on a top surface of a first portion of the metal level, wherein the via is tapered such that a smaller critical dimension is located at a top portion of the via and a larger critical dimension is located at a bottom portion of the via, and the bottom portion of the via is located directly on the top surface of the first portion of the metal level, and wherein the via includes an extension portion that extends parallel to the metal level and is located directly on the top surface of the first portion of the metal level; a dielectric cap located directly on a top surface of a second portion of the metal level on which the via is not located directly thereon; and a next metal level that is located directly on a top surface of the top portion of the via.
2 . The semiconductor structure of claim 1 , wherein the extension portion is terminated by the dielectric cap.
3 . The semiconductor structure of claim 1 , wherein the metal level includes sidewalls that are confined by an interlayer dielectric material.
4 . The semiconductor structure of claim 1 , wherein the metal level comprises ruthenium, tungsten, aluminum, cobalt, copper, manganese, titanium, or alloys thereof.
5 . The semiconductor structure of claim 1 , further comprising: a second metal level; a second via located directly on top of a first portion of the second metal level, wherein the second via is tapered such that a second smaller critical dimension is located at a top portion of the second via and a second larger critical dimension is located at a bottom portion of the second via, and the bottom portion of the second via is located adjacent the second metal level; a second dielectric cap located on top of a second portion of the second metal level on which the second via is not located directly thereon; and a second next metal level that is located directly on the top portion of the second via.
6 . The semiconductor structure of claim 5 , wherein the second via includes a second extension portion that extends along the second metal level.
7 . The semiconductor structure of claim 6 , wherein the second extension portion is terminated by the second dielectric cap.
8 . The semiconductor structure of claim 5 , wherein the second metal level includes sidewalls that are confined by an interlayer dielectric material.
9 . The semiconductor structure of claim 5 , wherein the second metal level comprises ruthenium, tungsten, aluminum, cobalt, copper, manganese, titanium, or alloys thereof.
10 . A semiconductor structure, comprising: a first metal line; a via located directly atop a top surface of the first metal line, and including an extended bottom portion that is located directly atop a first portion of the top surface of the first metal line and extends parallel to the first metal line; and a second metal line located directly atop the via.
11 . The semiconductor structure of claim 10 , wherein a dielectric cap is located directly atop a second portion of the first metal line and directly contacts a side of the extended bottom portion of the via.
12 . The semiconductor structure of claim 10 , wherein the first metal line includes sidewalls that are confined by an interlayer dielectric material.
13 . The semiconductor structure of claim 1 , wherein the via extends perpendicular to the metal level.
14 . The semiconductor structure of claim 10 , wherein the via extends perpendicular to the first metal line.

Description

BACKGROUND The present disclosure relates to fabrication methods and resulting structures for semiconductor devices. More particularly, the present disclosure provides a semiconductor structure with a top via having an extended bottom contact aligned to a metal line. Generally, semiconductor devices include a plurality of circuits which form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. For the IC device to be functional, multi-level or multi-layered interconnection schemes such as, for example, dual damascene wiring (interconnect structures) or wiring formed by subtractive etch, are fabricated using back end of line (BEOL) techniques to connect the circuit elements distributed on the surface of the device. Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. SUMMARY According to some embodiments of the disclosure, there is provided a semiconductor structure. The semiconductor structure includes a metal level, a via located directly on top of a first portion of the metal level, wherein the via is tapered such that a smaller critical dimension is located at a top portion of the via and a larger critical dimension is located at a bottom portion of the via, and the bottom portion of the via is located adjacent the metal level, a dielectric cap located on top of a second portion of the metal level on which the via is not located directly thereon, and a next metal level that is located directly on the top portion of the via. According to some embodiments of the disclosure, there is provided a semiconductor structure. The semiconductor structure includes a first metal line, a via including an extended bottom portion that is located atop a first portion of the first metal line and is aligned along a direction of the first metal line, and a second metal line located atop the via. According to some embodiments of the disclosure, there is provided a method of forming a semiconductor structure. The method includes an operation of forming an initial stack including an interconnect with a metal liner deposited on the interconnect, a metal level deposited on the metal liner, a dielectric cap deposited on the metal level, and a hard mask deposited on the dielectric cap. Another operation is subtractively cutting and patterning the initial stack to form a plurality of metal lines with portions of the dielectric cap and portions of the hard mask located thereon. A further operation is patterning a plurality of openings on top of the portions of the dielectric cap. Yet another operation is etching portions of the dielectric cap that are exposed within the plurality of openings and a portion of the dielectric cap extending laterally away from the plurality of openings. Another operation is filling the plurality of openings and etched portions of the dielectric cap to form a plurality of vias. A further operation is forming a plurality of next metal lines with one of the plurality of next metal lines being located on top of each of the plurality of vias. The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS The drawings included in the present application are incorporated into, and form part of, the specification. They illustrate embodiments of the present disclosure and, along with the description, serve to explain the principles of the disclosure. The drawings are only illustrative of certain embodiments and do not limit the disclosure. FIG. 1 illustrates a top view of a semiconductor structure disclosed herein and includes locations of where two cross-sections are taken (at X-X and at Y-Y) that are shown in cross-sectional views in the following FIGS. 2-9, in accordance with embodiments of the disclosure; FIG. 2 illustrates two cross-sectional views during formation of the semiconductor structure of FIG. 9, taken at X-X and Y-Y (as shown in FIG. 1) after a fabrication operation, in accordance with embodiments of the disclosure; FIG. 3 illustrates two cross-sectional views during formation of the semiconductor structure of FIG. 9, taken at X-X and Y-Y (as shown in FIG. 1) after a fabrication operation, in accordance with embodiments of the disclosure; FIG. 4 illustrates two cross-sectional views during formation of the semiconductor structure of FIG. 9, taken at X-X and Y-Y (as shown in FIG. 1) after a fabrication operation, in accordance with embodiments of the disclosure; FIG. 5 illustrates two cross-sectional views during formation of the semiconductor structure of FIG. 9, taken at X-