US-12628637-B2 - Back end of line interconnect structure

Abstract

Embodiments of the present disclosure include an interconnect structure having a via contact coupled to a middle of line (MOL) contact, a bottom of the via contact being free of a tantalum liner. A metal line is connected to the via contact, an interface between a top of the via contact and the metal line being free of the tantalum liner, the via contact and the metal line comprising copper, the via contact and the metal line being encapsulated with a cobalt liner.

Inventors

• Jim Shih-Chun Liang
• Pouya Hashemi
• Michael Robbins

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260512

Application Date

20231211

Claims (20)

1. 1 . An interconnect structure comprising: a via contact coupled to a middle of line (MOL) contact, a bottom of the via contact being free of a tantalum liner; and a metal line connected to the via contact, an interface between a top of the via contact and the metal line being free of the tantalum liner, the via contact and the metal line comprising copper, the via contact and the metal line being encapsulated with a cobalt liner.
2. 2 . The interconnect structure of claim 1 , wherein the via contact and the metal line are free of the tantalum liner further comprising nitride.
3. 3 . The interconnect structure of claim 1 , wherein the via contact and the metal line are free of a stack of another tantalum liner on top of the tantalum liner further comprising nitride.
4. 4 . The interconnect structure of claim 1 , wherein a cap layer encapsulates the cobalt liner.
5. 5 . The interconnect structure of claim 4 , wherein the cap layer comprises silicon carbide or a low-k dielectric material doped with nitrogen.
6. 6 . The interconnect structure of claim 4 , wherein the cap layer has a thickness ranging from about 0.1 nanometers (nm) to about 1 nm.
7. 7 . The interconnect structure of claim 1 , wherein a MOL cap layer is formed coplanar with a top surface of the MOL contact such that any misalignment of the via contact and the MOL contact causes a portion of the via contact to be disposed on the MOL cap layer.
8. 8 . The interconnect structure of claim 1 , wherein the MOL contact comprises tungsten.
9. 9 . A method for an interconnect structure comprising: forming a via contact on a middle of line (MOL) contact, such that a bottom of the via contact is free of a tantalum liner; and forming a metal line on the via contact, an interface between a top of the via contact and the metal line being free of the tantalum liner, the via contact and the metal line comprising copper, the via contact and the metal line being encapsulated with a cobalt liner.
10. 10 . The method of claim 9 , wherein the via contact and the metal line are free of the tantalum liner further comprising nitride.
11. 11 . The method of claim 9 , wherein the via contact and the metal line are free of a stack of another tantalum liner on top of the tantalum liner further comprising nitride.
12. 12 . The method of claim 9 , wherein a cap layer encapsulates the cobalt liner.
13. 13 . The method of claim 12 , wherein the cap layer comprises silicon carbide or a low-k dielectric material doped with nitrogen.
14. 14 . The method of claim 12 , wherein the cap layer has a thickness ranging from about 0.1 nanometers (nm) to about 1 nm.
15. 15 . The method of claim 9 , wherein a MOL cap layer is formed coplanar with a top surface of the MOL contact such that any misalignment of the via contact and the MOL contact causes a portion of the via contact to be disposed on the MOL cap layer.
16. 16 . The method of claim 9 , wherein the MOL contact comprises tungsten.
17. 17 . An interconnect structure comprising: a first via contact coupled to a middle of line (MOL) contact without a tantalum liner in between; a first metal line connected to the first via contact without the tantalum liner in between; a second via contact connected to the first metal line without the tantalum liner in between; and a second metal line connected to the second via contact without the tantalum liner in between, wherein the first via contact, the second via contact, the first metal line, and the second metal line comprise copper encapsulated with a cobalt liner.
18. 18 . The interconnect structure of claim 17 , wherein the first via contact, the second via contact, the first metal line, and the second metal line are free of the tantalum liner further comprising nitride.
19. 19 . The interconnect structure of claim 17 , wherein the first via contact, the second via contact, the first metal line, and the second metal line are free of a stack of another tantalum liner on top of the tantalum liner further comprising nitride.
20. 20 . The interconnect structure of claim 17 , wherein: a cap layer encapsulates the cobalt liner; the cap layer comprises silicon carbide or a low-k dielectric material doped with nitrogen; and the cap layer has a thickness ranging from about 0.1 nanometers (nm) to about 1 nm.

Description

BACKGROUND The present invention generally relates to fabrication methods and resulting structures for integrated circuits (ICs), and more specifically, to fabrication methods and resulting structures for back-end-of-line (BEOL) interconnect structures. ICs (also referred to as a chip or a microchip) include electronic circuits on a wafer. The wafer is a semiconductor material, such as, for example, silicon or other materials. An IC is formed of a large number of devices, such as transistors, capacitors, resistors, etc., which are formed in layers of the IC and interconnected with wiring in the BEOL layers of the wafer. Typical ICs are formed by first fabricating individual semiconductor devices using processes referred to generally as the front-end-of-line (FEOL). SUMMARY Embodiments of the present invention are directed to back-end-of-line (BEOL) interconnect structures. A non-limiting method of forming an interconnect structure. The method includes forming a via contact on a middle of line (MOL) contact, such that a bottom of the via contact is free of a tantalum liner. The method includes forming a metal line on the via contact, an interface between a top of the via contact and the metal line being free of the tantalum liner, the via contact and the metal line including copper, the via contact and the metal line being encapsulated with a cobalt liner. According to one or more embodiments, an interconnect structure includes a first via contact coupled to a middle of line (MOL) contact without a tantalum liner in between and a first metal line connected to the first via contact without the tantalum liner in between. The interconnect structures include a second via contact connected to the first metal line without the tantalum liner in between and a second metal line connected to the second via contact without the tantalum liner in between, where the first via contact, the second via contact, the first metal line, and the second metal line include copper encapsulated with a cobalt liner. Other embodiments of the present invention implement features of the above-described devices/structures in methods and/or implement features of the methods in devices/structures. Additional technical features and benefits are realized through the techniques of the present invention. Embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, refer to the detailed description and to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS The specifics of the exclusive rights described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: FIG. 1 depicts a cross-sectional view of a portion of an integrated circuit (IC) under-fabrication after fabrication operations according to one or more embodiments of the invention; FIG. 2 depicts a cross-sectional view of a portion of an IC under-fabrication after fabrication operations according to one or more embodiments of the invention; FIG. 3 depicts a cross-sectional view of a portion of an IC under-fabrication after fabrication operations according to one or more embodiments of the invention; FIG. 4 depicts a cross-sectional view of a portion of an IC under-fabrication after fabrication operations according to one or more embodiments of the invention; FIG. 5 depicts a cross-sectional view of a portion of an IC under-fabrication after fabrication operations according to one or more embodiments of the invention; FIG. 6 depicts a cross-sectional view of a portion of an IC under-fabrication after fabrication operations according to one or more embodiments of the invention; FIG. 7 depicts a cross-sectional view of a portion of an IC under-fabrication after fabrication operations according to one or more embodiments of the invention; FIG. 8 depicts a cross-sectional view of a portion of an IC under-fabrication after fabrication operations according to one or more embodiments of the invention; FIG. 9 depicts a cross-sectional view of a portion of an IC under-fabrication after fabrication operations according to one or more embodiments of the invention; FIG. 10 depicts a cross-sectional view of a portion of an IC under-fabrication after fabrication operations according to one or more embodiments of the invention; FIG. 11 depicts a cross-sectional view of a portion of an IC under-fabrication after fabrication operations according to one or more embodiments of the invention; FIG. 12 depicts a cross-sectional view of a portion of an IC under-fabrication after fabrication operations according to one or more embodiments of the invention; FIG. 13 depicts a cross-sectional view of a portion of an IC under-fabrication after fabrication operations according