US-12628638-B2 - Buried via-to-backside power rail (VBPR) for stacked field-effect transistor (FET)

Abstract

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first field-effect transistor (FET) having a first source/drain region is formed. A second FET having a second source/drain region is formed, where the second FET is stacked above the first FET. A trench extending from above the second source/drain region to beneath the first source/drain region is formed, where the trench passes through portions of (i) the first source/drain region and (ii) the second source/drain region. A bottom contact is formed in the trench. A dielectric layer is formed in the trench, the dielectric layer on a top surface of the bottom contact. A top contact is formed in the trench, the top contact on a top surface of the dielectric layer.

Inventors

• Ruilong Xie
• Nicholas Anthony Lanzillo
• Julien Frougier
• Kangguo Cheng
• Eric Miller
• Lawrence A Clevenger
• Daniel James Dechene

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260512

Application Date

20220510

Claims (18)

1. 1 . A semiconductor structure comprising: a first field-effect transistor (FET) having a first source/drain; a second FET having a second source/drain, wherein the second FET is stacked above the first FET; and a contact region extending from above the second source/drain to beneath the first source/drain, wherein: the contact region comprises a top contact, a bottom contact, and a dielectric layer; the dielectric layer (i) separates the top contact from the bottom contact and (ii) physically contacts both the top contact and the bottom contact along a plane parallel to a sidewall of the bottom contact; the dielectric layer and the bottom contact collectively pass completely through the first source/drain; and the first source/drain fully surrounds a portion of the sidewall of the bottom contact.
2. 2 . The semiconductor structure of claim 1 , wherein a bottom surface of the bottom contact contacts a backside power rail (BPR).
3. 3 . The semiconductor structure of claim 1 , wherein the dielectric layer separates: the bottom contact from the second source/drain; and the top contact from the first source/drain.
4. 4 . The semiconductor structure of claim 1 , wherein the top contact contacts a top surface of the second source/drain and a sidewall of the second source/drain.
5. 5 . The semiconductor structure of claim 1 , further comprising a second dielectric layer beneath the first source/drain.
6. 6 . The semiconductor structure of claim 1 , further comprising a buried oxide layer (BOX) beneath the first FET.
7. 7 . The semiconductor structure of claim 1 , further comprising a top surface of the top contact contacting a back end of line (BEOL) interconnect.
8. 8 . A method of forming a semiconductor structure, the method comprising: forming a first field-effect transistor (FET) having a first source/drain; forming a second FET having a second source/drain, wherein the second FET is stacked above the first FET; forming a trench extending from above the second source/drain to beneath the first source/drain, wherein the trench passes (i) completely through the first source/drain, such that a sidewall of the trench includes a fully surrounding portion of a sidewall of the first source/drain, and (ii) through portions of the second source/drain; forming a bottom contact in the trench; forming a dielectric layer in the trench, the dielectric layer on a top surface of the bottom contact; and forming a top contact in the trench, the top contact on a top surface of the dielectric layer, wherein the dielectric layer (i) separates the top contact from the bottom contact and (ii) physically contacts both the top contact and the bottom contact along a plane parallel to the sidewall of the first source/drain.
9. 9 . The method of claim 8 , wherein the bottom contact contacts the fully surrounding portion of the sidewall of the first source/drain.
10. 10 . The method of claim 8 , wherein the dielectric layer separates: the bottom contact from the second source/drain; and the top contact from the first source/drain.
11. 11 . The method of claim 8 , further comprising: prior to forming the top contact, forming additional material for the second source/drain by epitaxial growth of a semiconductor material on physically exposed sidewalls of the second source/drain.
12. 12 . The method of claim 8 , further comprising: prior to forming the top contact, a second trench exposing a top surface of the second source/drain, wherein forming the top contact further comprises, forming the top contact in the second trench.
13. 13 . The method of claim 8 , wherein a top surface of the top contact contacts a back end of line (BEOL) interconnect.
14. 14 . The method of claim 13 , further comprising: bonding a top surface of the BEOL interconnect to a carrier wafer; flipping the semiconductor structure; and forming a backside power rail (BPR), wherein the BPR contacts a bottom surface of the bottom contact.
15. 15 . The method of claim 8 , wherein forming the first FET and the second FET comprises: providing a bottom nanosheet stack and a top nanosheet stack separated by a spacer, each nanosheet stack comprising alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet, wherein a sacrificial gate structure straddles over the bottom nanosheet stack and the top nanosheet stack; forming the first source/drain by epitaxial growth of a semiconductor material on physically exposed sidewalls of each semiconductor channel material nanosheet of the bottom nanosheet stack, wherein the first source/drain is present on a surface of the dielectric layer; forming an interlayer dielectric layer on the first source/drain; forming the second source/drain by epitaxial growth of a semiconductor material on physically exposed sidewalls of each semiconductor channel material nanosheet of the top nanosheet stack, wherein the second source/drain is present on the interlayer dielectric layer; removing the sacrificial gate structure; removing each sacrificial semiconductor material nanosheet of the top nanosheet stack and the bottom nanosheet stack to suspend each semiconductor channel material nanosheet of the top nanosheet stack and the bottom nanosheet stack; and forming a functional gate structure in regions occupied by the sacrificial gate structure and each sacrificial semiconductor material nanosheet, wherein the functional gate structure wraps around each suspended semiconductor channel material nanosheet.
16. 16 . The method of claim 8 , further comprising: prior to forming the first source/drain and the second source/drain: recessing exposed portions of a buried oxide layer (BOX) beneath the first FET; and forming a second dielectric layer in the recess of the BOX.
17. 17 . The method of claim 15 , further comprising: flipping the semiconductor structure; removing the sacrificial gate structure; selectively etching expose portions of the second dielectric layer; and forming a metal bottom contact in an area previously occupied by the sacrificial gate structure and the selectively etched portions of the second dielectric layer.
18. 18 . The method of claim 17 , further comprising forming a backside power rail (BPR), wherein the BPR contacts a bottom surface of the metal bottom contact.

Description

BACKGROUND The present invention relates generally to the field of semiconductor devices and fabrication, and more particularly to stacked integrated circuit structures, containing field-effect transistors (FETs), having a buried via-to-backside power rail (VBPR) that connects bottom source/drain (S/D) of the stacked device to backside power rail (BPR), with a dielectric layer isolating an upper contact from the VBPR. The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. One type of non-planar semiconductor device that has been touted as a viable option beyond the 7 nm technology node is a nanosheet containing device. By “nanosheet containing device” it is meant that the device contains one or more layers of semiconductor channel material portions having a vertical thickness that is substantially less than its width. Nanosheet formation relies on the selective removal of one semiconductor material (e.g., silicon) to another semiconductor material (e.g., a silicon germanium alloy) to form suspended nanosheets for gate-all-around devices. Source/drain (S/D) regions for nanosheet containing devices are currently formed by epitaxial growth of a semiconductor material upwards from an exposed surface of the semiconductor substrate and from sidewalls of each nanosheet. A stacked device is formed by stacking one FET over another FET, greatly reducing the footprint of the device and increase the transistor density. SUMMARY Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. The method includes forming a first field-effect transistor (FET) having a first source/drain region. The method can also include forming a second FET having a second source/drain region, where the second FET is stacked above the first FET. The method can also include forming a trench extending from above the second source/drain region to beneath the first source/drain region, where the trench passes through portions of (i) the first source/drain region and (ii) the second source/drain region. The method can also include forming a bottom contact in the trench. The method can also include forming a dielectric layer in the trench, the dielectric layer on a top surface of the bottom contact. The method can also include forming a top contact in the trench, the top contact on a top surface of the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A depicts a top-down view, FIG. 1B depicts a cross-sectional view, along section line B of FIG. 1A, and FIG. 1C depicts a cross-sectional view, along section line C of FIG. 1A, of a device at an early stage in the method of forming the device, the device including a stacked field-effect transistor (FET) front end of line (FEOL) formation upon which embodiments of the present invention can be fabricated, in accordance with an embodiment of the invention. FIG. 2A depicts a top-down view, FIG. 2B depicts a cross-sectional view, along section line B of FIG. 2A, and FIG. 2C depicts a cross-sectional view, along section line C of FIG. 2A, of a process of forming middle of line (MOL) interlayer dielectric (ILD) material, in accordance with an embodiment of the invention. FIG. 3A depicts a top-down view, FIG. 3B depicts a cross-sectional view, along section line B of FIG. 3A, and FIG. 3C depicts a cross-sectional view, along section line C of FIG. 3A, of a process for forming reverse body bias voltage (VBPR) contact trenches, in accordance with an embodiment of the present invention. FIG. 4A depicts a top-down view, FIG. 4B depicts a cross-sectional view, along section line B of FIG. 4A, and FIG. 4C depicts a cross-sectional view, along section line C of FIG. 4A, of a process of forming recessed VBPR contacts, in accordance with an embodiment of the present invention. FIG. 5A depicts a top-down view, FIG. 5B depicts a cross-sectional view, along section line B of FIG. 5A, and FIG. 5C depicts a cross-sectional view, along section line C of FIG. 5A, of a process of forming a VBPR dielectric cap, in accordance with an embodiment of the present invention. FIG. 6A depicts a top-down view, FIG. 6B depicts a cross-sectional view, along section line B of FIG. 6A, and FIG. 6C depicts a cross-sectional view, along section line C of FIG. 6A, of a process of forming additional top source/drain material, in accordance with an embodiment of the present invention. FIG. 7A depicts a top-down view, FIG. 7B depicts a cross-sectional view, along section line B of FIG. 7A, and FIG. 7C depicts a cross-sectional view, along section line C of FIG. 7A, of a process of forming MOL contact trenches, in accordance with an embodiment of the present invention. FIG. 8A depicts a top-down view, FIG. 8B depicts a cross-sectional view, along section line B of FIG. 8A, and FIG. 8C depicts a cross-sectional view, along section l