US-12628639-B2 - Power gating switch tree structure for reduced wake-up time and power leakage

Abstract

An aspect relates to an apparatus including a first and second power rails; a first set of power switch cells coupled to the first and second power rails, the first set of power switch cells being cascaded from an output to an input of a control circuit; and a second set of power switch cells coupled to the first and second power rails, the second set of power switch cells being coupled to one of a pair of cells of the first set, the first output, and the first input of the control circuit. Another aspect relates to a method including propagating a control signal via a first set of cascaded power switch cells to sequentially couple a first power rail to a second power rail; and propagating the control signal via a second set of power switch cells coupled between a pair of cells of the first set.

Inventors

• Yuehui Wang

Assignees

• QUALCOMM INCORPORATED

Dates

Publication Date

20260512

Application Date

20230424

Claims (20)

1. 1 . An apparatus, comprising: a first power rail; a second power rail; a control circuit including a first input, a first output, a second input, and a second output; a first set of power switch cells coupled to the first and second power rails, wherein the first set of power switch cells are cascaded from the first output to the first input of the control circuit in accordance with a first cell-to-cell routing, and wherein at least a portion of the first set of power switch cells are cascaded from the second output to the second input of the control circuit in accordance with a second cell-to-cell routing, the second cell-to-cell routing being different than the first cell-to-cell routing; and a second set of at least one power switch cell coupled to the first and second power rails, wherein the second set of at least one power switch cell is coupled to one of a first node between a first pair of power switch cells of the first set, the first output of the control circuit, and the first input of the control circuit.
2. 2 . The apparatus of claim 1 , wherein the second set of at least one power switch cell comprises a second set of cascaded power switch cells extending from one of: the first node, the first output of the control circuit, and the first input of the control circuit.
3. 3 . The apparatus of claim 2 , further comprising a third set of at least one power switch cell coupled to the first and second power rails, wherein the third set of at least one power switch cell is coupled to a second node between a second pair of power switch cells of the second set.
4. 4 . The apparatus of claim 3 , wherein the third set of at least one power switch cell does not precede another power switch cell.
5. 5 . The apparatus of claim 4 , wherein the third set of at least one power switch cell comprises: a first buffer or inverter including a first input coupled to a first output of one of the second set of cascaded power switch cells; a first field effect transistor (FET) coupled between the first and second power rails, wherein the first FET includes a first gate coupled to a first output of the first buffer or inverter; a second buffer or inverter including a second input coupled to a second output of the one of the second set of cascaded power switch cells; and a second FET coupled between the first and second power rails, wherein the second FET includes a second gate coupled to a second output of the second buffer or inverter, and wherein the second FET is larger than the first FET.
6. 6 . The apparatus of claim 1 , wherein each of the first set of cascaded power switch cells comprises: a first buffer or inverter including a first input coupled to one of a first output of a preceding one of the first set of cascaded power switch cells and the first output of the control circuit; a first field effect transistor (FET) coupled between the first and second power rails, wherein the first FET includes a first gate coupled to a first output of the first buffer or inverter; a second buffer or inverter including a second input coupled to a second output of one of the preceding one of the first set of cascaded power switch cells and the second output of the control circuit; a second FET coupled between the first and second power rails, wherein the second FET includes a second gate coupled to a second output of the second buffer or inverter, and wherein the second FET is larger than the first FET; a third buffer or inverter including a third input coupled to the first gate of the first FET, and a third output coupled to one of a first input of a following one of the first set of cascaded power switch cells or the first input of the control circuit; and a fourth buffer or inverter including a fourth input coupled to the second gate of the second FET, and a fourth output coupled to one of a second input of the following one of the first set of cascaded power switch cells and the second input of the control circuit.
7. 7 . The apparatus of claim 1 , wherein at least one of the first set of cascaded power switch cells or at least one of the second set of at least one power switch cell, comprises: a first buffer or inverter including a first input coupled to one of a first output of a preceding power switch cell and the first output of the control circuit; a first field effect transistor (FET) coupled between the first and second power rails, wherein the first FET includes a first gate coupled to a first output of the first buffer or inverter; a second buffer or inverter including a second input coupled to one of a second output of the or another preceding power switch cell and the second output of the control circuit; a second FET coupled between the first and second power rails, wherein the second FET includes a second gate coupled to a second output of the second buffer or inverter, and wherein the second FET is larger than the first FET; and a third buffer or inverter including a third input coupled to the first gate of the first FET, and a third output coupled to one of a first input of the following power switch cell and the first input of the control circuit, wherein the second gate is coupled to a floating output.
8. 8 . The apparatus of claim 1 , wherein at least one of the first set of cascaded power switch cells or at least one of the second set of at least one power switch cell, comprises: a first buffer or inverter including a first input coupled to one of a first output of a preceding power switch cell and the first output of the control circuit; a first field effect transistor (FET) coupled between the first and second power rails, wherein the first FET includes a first gate coupled to a first output of the first buffer or inverter; a second buffer or inverter including a second input coupled to one of a second output of the or another preceding power switch cell and the second output of the control circuit; a second FET coupled between the first and second power rails, wherein the second FET includes a second gate coupled to a second output of the second buffer or inverter, and wherein the second FET is larger than the first FET; and a third buffer or inverter including a third input coupled to the second gate of the second FET, and a third output coupled to one of a first input of the following or another power switch cell and the second input of the control circuit, wherein the first gate is coupled to a floating output.
9. 9 . The apparatus of claim 1 , wherein the second set of at least one power switch cell comprises a set of parallel power switch cells.
10. 10 . The apparatus of claim 9 , wherein each of the set of parallel power switch cells does not precede another power switch cell.
11. 11 . The apparatus of claim 10 , wherein each of the set of parallel power switch cells comprises: a first buffer or inverter including a first input coupled to one of a first output of a preceding power switch cell of the first set and the first output of the control circuit; a first field effect transistor (FET) coupled between the first and second power rails, wherein the first FET includes a first gate coupled to a first output of the first buffer or inverter; a second buffer or inverter including a second input coupled to one of a second output of the preceding power switch cell and the second output of the control circuit; and a second FET coupled between the first and second power rails, wherein the second FET includes a second gate coupled to a second output of the second buffer or inverter, and wherein the second FET is larger than the first FET.
12. 12 . The apparatus of claim 1 , wherein each of the first set of power switch cells comprises: a first input coupled to one of the first output of the control circuit and a first output of the preceding power switch cell of the first set; a first output coupled to one of the first input of the control circuit and a first input of the following power switch cell of the first set; a second input coupled to one of the second output of the control circuit and a second output of the preceding power switch cell of the first set; and a second output coupled to one of the second input of the control circuit and a second input of the following power switch cell of the first set.
13. 13 . The apparatus of claim 1 , wherein at least one of the first set of power switch cells comprises: a first input coupled to one of the first output of the control circuit and a first output of the preceding power switch cell of the first set; a first output coupled to one of the first input of the control circuit and a first input of the following power switch cell of the first set; a second input coupled to one of the second output of the control circuit, a second output of the preceding power switch cell of the first set, and a third output of a first power switch cell not in the first set; and a second output coupled to one of the second input of the control circuit, a second input of the following power switch cell of the first set, and a third input of a second power switch cell not in the first set.
14. 14 . The apparatus of claim 1 , wherein at least one of the second set of power switch cells comprises: a first input coupled to one of the first output of the control circuit, a first output of the preceding power switch cell of the first set, and a second output of the preceding power switch cell of the second set; and a second input coupled to one of the second output of the control circuit, a second output of the preceding power switch cell of the first set, and a third output of the preceding power switch cell of the second set.
15. 15 . The apparatus of claim 1 , wherein the second set of at least one power switch cell comprises a second set of power switch cells cascaded from the first input of the control circuit in accordance with a third cell-to-cell routing, and wherein the second set of power switch cells are cascaded from the second input of the control circuit in accordance with a fourth cell-to-cell routing being different than the third cell-to-cell routing.
16. 16 . A method, comprising: propagating a first control signal via a first set of cascaded power switch cells from a first output to a first input of a control circuit in accordance with a first cell-to-cell routing to sequentially couple a first power rail to a second power rail, wherein the second power rail is coupled to a circuit; propagating a second control signal via at least a portion of the first set of cascaded power switch cells from a second output to a second input of the control circuit in accordance with a second cell-to-cell routing to sequentially couple the first power rail to the second power rail, wherein the second cell-to-cell routing is different than the first cell-to-cell routing; and propagating the first control signal via a second set of at least one power switch cell coupled between a first pair of power switch cells of the first set to couple the first power rail to the second power rail; wherein the second set of at least one power switch cell comprises a set of parallel power switch cells, and wherein propagating the first control signal via the second set of at least one power switch cell comprises propagating the first control signal via the set of parallel power switch cells to couple the first power rail to the second power rail.
17. 17 . The method of claim 16 , wherein propagating the first control signal via a second set of at least one power switch cell comprises propagating the first control signal via a second set of cascaded power switch cells in accordance with a third cell-to-cell routing, and further comprising propagating the second control signal via the second set of cascaded power switch cells in accordance with a fourth cell-to-cell routing, the fourth cell-to-cell routing being different than the third cell-to-cell routing.
18. 18 . An apparatus, comprising: means for propagating a first control signal via a first set of cascaded power switch cells from a first output to a first input of a control circuit in accordance with a first cell-to-cell routing to sequentially couple a first power rail to a second power rail, wherein the second power rail is coupled to a circuit; means for propagating a second control signal via at least a portion of the first set of cascaded power switch cells from a second output to a second input of the control circuit in accordance with a second cell-to-cell routing to sequentially couple the first power rail to the second power rail, wherein the second cell-to-cell routing is different than the first cell-to-cell routing; and means for propagating the first control signal via a second set of at least one power switch cell coupled between a first pair of power switch cells of the first set to couple the first power rail to the second power rail; wherein the second set of at least one power switch cell comprises a set of parallel power switch cells, and wherein the means for propagating the first control signal via the second set of at least one power switch cell comprises means for propagating the first control signal via the second set of parallel power switch cells to couple the first power rail to the second power rail.
19. 19 . A wireless communication device, comprising: at least one antenna; a transceiver coupled to the at least one antenna; a signal processing core coupled to the transceiver; a first power rail; a second power rail coupled to the signal processing core; a control circuit including a first input, a first output, a second input, and a second output; a first set of cascaded power switch cells coupled to the first and second power rails, wherein the first set of power switch cells are cascaded from the first output to the first input of the control circuit in accordance with a first cell-to-cell routing, and wherein at least a portion of the first set of power switch cells are cascaded from the second output to the second input of the control circuit in accordance with a second cell-to-cell routing, the second cell-to-cell routing being different than the first cell-to-cell routing; and a second set of at least one power switch cell coupled to the first and second power rails, wherein the second set of at least one power switch cell is coupled to one of a first node between a first pair of power switch cells of the first set, the first output of the control circuit, and the first input of the control circuit.
20. 20 . The wireless communication device of claim 19 , wherein the second set of at least one power switch cell comprises a second set of cascaded power switch cells extending from one of the first node, the first output of the control circuit, and the first input of the control circuit.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present Application for Patent is a Divisional of pending U.S. Non-Provisional application Ser. No. 17/331,450, filed May 26, 2021, and assigned to the assignee hereof and hereby expressly incorporated by reference herein as if fully set forth below and for all applicable purposes. FIELD Aspects of the present disclosure relate generally to power gating circuits, and in particular, to a power gating switch tree structure for reduced wake-up time and power leakage. BACKGROUND An integrated circuit (IC) typically includes multiple cores, such as a central processing unit (CPU) core, graphics processing unit (GPU) core, modem core, imaging (camera) core, memory core, etc. A power management integrated circuit (PMIC) may supply power (e.g., supply voltage and current) to the IC; and more, specifically, to a global power rail of the IC for further distribution therein. The IC may also include a power gating circuit for selectively coupling the global power rail to local power rails coupled to the various cores, respectively. The power gating circuit should be configured to selectively couple the global power rail to a local power rail without significantly affecting IC cores already coupled to the global power rail. SUMMARY The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later. An aspect of the disclosure relates to an apparatus. The apparatus includes a first power rail; a second power rail; a control circuit including a first input and a first output; a first set of power switch cells coupled to the first and second power rails, wherein the first set of power switch cells are cascaded from the first output to the first input of the control circuit; and a second set of at least one power switch cell coupled to the first and second power rails, wherein the second set of at least one power switch cell is coupled to one of a first node between a first pair of power switch cells of the first set, the first output of the control circuit, and the first input of the control circuit. Another aspect of the disclosure relates to a method. The method includes propagating a first control signal via a first set of cascaded power switch cells to sequentially couple a first power rail to a second power rail, wherein the second power rail is coupled to a circuit; and propagating the first control signal via a second set of at least one power switch cell coupled between a first pair of power switch cells of the first set to couple the first power rail to the second power rail. Another aspect of the disclosure relates to an apparatus. The apparatus includes means for propagating a first control signal via a first set of cascaded power switch cells to sequentially couple a first power rail to a second power rail, wherein the second power rail is coupled to a circuit; and means for propagating the first control signal via a second set of at least one power switch cell coupled between a first pair of power switch cells of the first set to couple the first power rail to the second power rail. Another aspect relates to a wireless communication device. The wireless communication device includes at least one antenna; a transceiver coupled to the at least one antenna; a signal processing core coupled to the transceiver; a first power rail; a second power rail coupled to the signal processing core; a control circuit including a first input and a first output; a first set of cascaded power switch cells coupled to the first and second power rails, wherein the first set of power switch cells are cascaded from the first output to the first input of the control circuit; and a second set of at least one power switch cell coupled to the first and second power rails, wherein the second set of at least one power switch cell is coupled to one of a first node between a first pair of power switch cells of the first set, the first output of the control circuit, and the first input of the control circuit. To the accomplishment of the foregoing and related ends, the one or more implementations include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of various implementations may be employed and the description implementations are intended to include all such aspects and their equiv