US-12628640-B2 - Metal line profile shaping for advanced integrated circuit structure fabrication

US12628640B2US 12628640 B2US12628640 B2US 12628640B2US-12628640-B2

Abstract

Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a dielectric material structure having a trench therein. A conductive interconnect line in the trench, the conductive interconnect line having a length and a width, the width having a cross-sectional profile, wherein the cross-sectional profile of the width of the conductive interconnect line has a bottom lateral width, a mid-height lateral width, and a top lateral width, and wherein the mid-height lateral width is greater than the bottom lateral width, and the mid-height lateral width is greater than the top lateral width.

Inventors

Leonard P. GULER
Tsuan-Chung CHANG
Michael James MAKOWSKI
Benjamin Kriegel
Robert Joachim
Desalegne B. Teweldebrhan
Charles H. Wallace
Tahir Ghani
Mohammad Hasan

Assignees

INTEL CORPORATION

Dates

Publication Date: 20260512
Application Date: 20210624

Claims (4)

1 . An integrated circuit structure, comprising: a dielectric material structure having a trench therein; a conductive interconnect line in the trench, the conductive interconnect line having a length and a cross-sectional profile orthogonal to the length, wherein the cross-sectional profile is a circular cross-sectional profile, wherein the circular cross-sectional profile has a bottom lateral width, a mid-height lateral width, and a top lateral width, and wherein the mid-height lateral width is greater than the bottom lateral width, and the mid-height lateral width is greater than the top lateral width; and a conductive via coupled to conductive interconnect line, the conductive via having a center laterally offset from a center of the conductive line along a vertical axis, and the conductive via on a top and along a first side of the conductive interconnect line but not along a second side of the conductive line, the second side laterally opposite the first side.
2 . The integrated circuit structure of claim 1 , wherein the mid-height lateral width is at least 50% greater than the bottom lateral width and at least 50% greater than the top lateral width.
3 . The integrated circuit structure of claim 1 , wherein the circular cross-sectional profile has one or more scalloped surfaces.
4 . The integrated circuit structure of claim 1 , wherein the dielectric material structure comprises a stack of dielectric layers of differing composition.

Description

TECHNICAL FIELD Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, metal line profile shaping and the resulting structures. BACKGROUND For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant. Variability in conventional and currently known fabrication processes may limit the possibility to further extend them into the 10 nanometer node or sub-10 nanometer node range. Consequently, fabrication of the functional components needed for future technology nodes may require the introduction of new methodologies or the integration of new technologies in current fabrication processes or in place of current fabrication processes. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1-5 illustrate cross-sectional views representing various operations in a method of fabricating an integrated circuit structure, in accordance with an embodiment of the present disclosure. FIG. 6A illustrates cross-sectional views representing a landed via and an unlanded via for conventional conductive interconnects, and FIG. 6B illustrates cross-sectional views representing a landed via and an unlanded via for shaped conductive interconnects, in accordance with an embodiment of the present disclosure. FIG. 7 illustrates a cross-sectional view of a metallization layer fabricated using pitch halving scheme above a metallization layer fabricated using pitch quartering scheme, in accordance with an embodiment of the present disclosure. FIG. 8 illustrates a cross-sectional view of an integrated circuit structure having a metallization layer with a metal line composition above a metallization layer with a differing metal line composition, in accordance with an embodiment of the present disclosure. FIG. 9 illustrates a cross-sectional view of an integrated circuit structure having a metallization layer with a metal line composition coupled to a metallization layer with a differing metal line composition, in accordance with an embodiment of the present disclosure. FIG. 10 illustrates a cross-sectional view of an integrated circuit structure having four metallization layers with a metal line composition and pitch above two metallization layers with a differing metal line composition and smaller pitch, in accordance with an embodiment of the present disclosure. FIG. 11 illustrates a computing device in accordance with one implementation of the disclosure. FIG. 12 illustrates an interposer that includes one or more embodiments of the disclosure. FIG. 13 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or more features described herein, in accordance with an embodiment of the present disclosure. FIG. 14 illustrates a cross-sectional view of a flip-chip mounted die, in accordance with an embodiment of the present disclosure. DESCRIPTION OF THE EMBODIMENTS Metal line profile shaping and the resulting structures are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description. This specification includes references to “one embodiment” or “an embodiment.” The appearances of the phrases “in one embodim