US-12628641-B2 - Memory device and manufacturing method of the memory device

Abstract

There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a stack structure including gate lines stacked to be spaced apart from each other; main plugs arranged to be spaced apart from each other; plug isolation patterns isolating the main plugs into first and second sub-plugs; and a select isolation pattern isolating at least one gate line located between the plug isolation patterns adjacent to each other.

Inventors

• Won Geun CHOI
• Jeong Hwan Kim
• Mi Seong PARK
• Jung Shik JANG

Assignees

• SK Hynix Inc.

Dates

Publication Date

20260512

Application Date

20230111

Priority Date

20220602

Claims (14)

1. 1 . A memory device comprising: a stack structure including a plurality of gate lines stacked in a vertical direction over a source line, the plurality of gate lines spaced apart from each other in the vertical direction; main plugs arranged to be spaced apart from each other in a direction parallel to the plurality of gate lines; plug isolation patterns isolating the main plugs into first and second sub-plugs; and a select isolation structure comprising a select isolation pattern together with the plug isolation pattern, wherein the plurality of gate lines include at least one cell gate line and at least on select line, wherein the select isolation pattern penetrates at least one select line, to divide the at least one select line into a first select line and a second select line formed in the same level, and wherein the select isolation structure extends in a direction vertical to a direction in which the first sub-plug and the second sub-plug are arranged.
2. 2 . The memory device of claim 1 , wherein the plug isolation patterns disposed between the first sub-plug and the second sub-plug.
3. 3 . The memory device of claim 2 , wherein each of the first and second sub-plugs includes a core pillar, a channel layer, a tunnel insulating layer, a charge trap layer, and a blocking layer, which are formed in the vertical direction.
4. 4 . The memory device of claim 1 , wherein the plug isolation patterns are formed of an insulating material.
5. 5 . The memory device of claim 1 , wherein the plug isolation patterns penetrate the main plugs and the stack structure.
6. 6 . The memory device of claim 1 , wherein the select isolation pattern along with the plug isolation patterns adjacent to each other isolates the at least one select line, from the plurality of gate lines, into a first drain select line and a second drain select line formed in the same level.
7. 7 . The memory device of claim 1 , wherein the select isolation pattern penetrates at least a portion of the plug isolation patterns adjacent to each other.
8. 8 . The memory device of claim 1 , wherein the select isolation pattern is formed in one of a circular or an elliptical shape partially overlapping with the plug isolation patterns adjacent to each other.
9. 9 . The memory device of claim 1 , wherein the select isolation pattern is formed of an insulating material.
10. 10 . The memory device of claim 1 , wherein the stack structure is isolated by the select isolation pattern and the plug isolation patterns.
11. 11 . The memory device of claim 1 , wherein the select isolation pattern contacts with the plug isolation patterns adjacent to each other.
12. 12 . The memory device of claim 1 , wherein the gate lines include source select lines, word lines and drain select lines which are stacked to be spaced apart from each other, and wherein the drain select lines are isolated by the select isolation pattern and the plug isolation patterns into the first and second drain select lines.
13. 13 . The memory device of claim 1 , wherein the select isolation structure isolates the plurality of gate lines by cooperation between the select isolation pattern and the plug isolation patterns.
14. 14 . The memory device of claim 1 , wherein each of the plug isolation patterns fully penetrates the main plugs in the vertical direction.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2022-0067784 filed on Jun. 2, 2022, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein. BACKGROUND 1. Technical Field The present disclosure generally relates to a memory device and a manufacturing method of the memory device, and more particularly, to a three-dimensional memory device and a manufacturing method of the three-dimensional memory device. 2. Related Art A memory device may be classified into a volatile memory device in which stored data disappears when the supply of power is interrupted and a nonvolatile memory device in which stored data is retained even when the supply of power is interrupted. The nonvolatile memory device may include a NAND flash memory, a NOR flash memory, a resistive random access memory (ReRAM), a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), and the like. A NAND flash memory system may include a memory device configured to store data and a controller configured to control the memory device. The memory device may include a memory cell array in which data is stored and peripheral circuits configured to perform a program, read or erase operation in response to a command transmitted from the controller. The memory cell array may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of memory cells. As the degree of integration of memory devices increases, a memory device capable of storing large-capacity data is required, and simplification of manufacturing processes is required to reduce manufacturing cost. SUMMARY In accordance with an aspect of the present disclosure, there is provided a memory device including: a stack structure including gate lines stacked to be spaced apart from each other; main plugs arranged to be spaced apart from each other; plug isolation patterns isolating the main plugs into first and second sub-plugs; and a select isolation pattern isolating at least one gate line located between the plug isolation patterns adjacent to each other. In accordance with another aspect of the present disclosure, there is provided a method of manufacturing a memory device, the method including: forming, a lower structure, a stack structure including gate lines, main plugs arranged in a vertical direction, and plug isolation patterns isolating the main plugs into first and second sub-plugs; forming a second isolation hole isolating at least one gate line, the second isolation hole formed between the plug isolation patterns; and forming a select isolation pattern inside the second isolation hole. BRIEF DESCRIPTION OF THE DRAWINGS Examples of embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. In the drawing figures, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout. FIG. 1 is a diagram illustrating a memory device in accordance with an embodiment of the present disclosure. FIG. 2 is a diagram illustrating an arrangement structure of a memory cell array and a peripheral circuit. FIG. 3 is a diagram illustrating a structure of the memory cell array. FIG. 4 is a view illustrating a layout of a memory device in accordance with an embodiment of the present disclosure. FIG. 5 is a layout illustrating a structure of a plug region in accordance with an embodiment of the present disclosure. FIG. 6 is a sectional view illustrating a structure of the plug region in accordance with an embodiment of the present disclosure. FIG. 7 is a layout illustrating a structure of a select isolation pattern region in accordance with an embodiment of the present disclosure. FIG. 8 is a sectional view illustrating a structure of the select isolation pattern region in accordance with an embodiment of the present disclosure. FIGS. 9A, 9B, 9C, 9D, 9E, 9F, 9G, 9H, 9I, and 9J are layouts illustrating a manufacturing method of a memory device in accordance with an embodiment of the present disclosure. FIGS. 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10I, and 10J are sectional views in a y-axis direction, illustrating a manufacturing method of a memory device in accordance with an embodiment of the present disclosure. FIGS. 11A, 11B, 11C, 11D, 11E, 11F, 11G, 11H, 11I, and 11J are sectional views in an x-axis direction, illustrating a manufacturing method of a memory device in acco