US-12628642-B2 - Circuit structure including at least one air gap and method for manufacturing the same

US12628642B2US 12628642 B2US12628642 B2US 12628642B2US-12628642-B2

Abstract

A circuit structure and a method of manufacturing a circuit structure are provided. The circuit structure includes a first metal line and a second metal line. The second metal line is disposed over the first metal line. At least one air gap is disposed between the first metal line and the second metal line.

Inventors

Hsih-Yang Chiu

Assignees

NANYA TECHNOLOGY CORPORATION

Dates

Publication Date: 20260512
Application Date: 20230306

Claims (7)

1 . A circuit structure, comprising: a first metal line; a second metal line disposed over the first metal line, wherein at least one air gap is disposed between the first metal line and the second metal line; a first dielectric layer which is a solid layer, wherein the first metal line is embedded in the first dielectric layer, wherein the first dielectric layer is made of oxide material or nitride material; a second dielectric layer, which is a solid layer, having a plurality of portions spaced apart from each other, wherein the portions of the second dielectric layer are separated by the air gap; a plurality of supporting portions embedded in the second dielectric layer and formed between the portions of the second dielectric layer; a mask layer disposed between an intermediate dielectric layer and the second dielectric layer, wherein a bottom surface of the second dielectric layer is in contact with a top surface of the mask layer; and the intermediate dielectric layer, wherein a top surface of the first metal line is coplanar with a top surface of the first dielectric layer, wherein the intermediate dielectric layer is disposed on and in contact with the top surface of the first metal line and the top surface of first dielectric layer so as to cover the first metal line and the first dielectric layer; wherein the second metal line comprises a first layer, a second layer and a third layer stacked on one another to form a patterned circuit layer, wherein a top surface of the third layer is coplanar with a top surface of the second dielectric layer; wherein the air gap is enclosed by two inner surfaces of the portions of the second dielectric layer and a bottom surface of the first layer; wherein the plurality of supporting portions are spaced apart from each other to define the air gap, such that the air gap is further defined by an inner surface of one of the supporting portions, wherein each of the supporting portions is in contact with the bottom surface of the first layer; wherein a thickness of one of the plurality of supporting portions is substantially equal to a height of the at least one air gap; wherein the intermediate dielectric layer is disposed between the first dielectric layer and the second dielectric layer, wherein the intermediate dielectric layer is disposed on the top surface of the first dielectric layer to cover and to contact with the top surface of the first metal line; wherein the at least one air gap is defined by the top surface of the mask layer and the bottom surface of the second metal line.
2 . The circuit structure of claim 1 , wherein the plurality of supporting portions support the second metal line, wherein a bottom surface of each of the supporting portions is coplanar with a bottom surface of the second dielectric layer, wherein a thickness of the second dielectric layer is equal to a sum of a thickness of the second metal line and a height of each of the supporting portions.
3 . The circuit structure of claim 1 , wherein a third width of one of the plurality of supporting portions is substantially equal to a second width of the at least one air gap from a top view.
4 . The circuit structure of claim 1 , wherein a third width of one of the plurality of supporting portions is substantially equal to a first width of the second metal line from a top view.
5 . The circuit structure of claim 1 , wherein a first lateral surface of one of the plurality of supporting portions is substantially aligned with a second lateral surface of the second metal line and is contact with one of the two inner surfaces of the portions of the second dielectric layer.
6 . The circuit structure of claim 1 , wherein a first width of the second metal line is substantially equal to a second width of the at least one air gap from a top view, wherein the first metal line is embedded in the first dielectric layer at a position that a bottom surface of the first metal line is positioned above a bottom surface of the first dielectric layer.
7 . The circuit structure of claim 1 , wherein each of the first dielectric layer and the second dielectric layer is made of dielectric material comprising oxide material or nitride material.

Description

TECHNICAL FIELD The present disclosure relates to a circuit structure and a method for manufacturing a circuit structure, and more particularly, to a circuit structure including at least one air gap. DISCUSSION OF THE BACKGROUND In a circuit structure, an upper metal line may be disposed over a lower metal line. An undesired parasitic capacitance may occur between the upper metal line and the lower metal line. Such parasitic capacitance may adversely affect the speed response of the circuit structure. As electronic devices are scaled down and the gap the upper metal line and the lower metal line is getting smaller, signal loss due to parasitic capacitance will become an increasingly critical concern. This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed herein constitutes prior art with respect to the present disclosure, and no part of this Discussion of the Background may be used as an admission that any part of this application constitutes prior art with respect to the present disclosure. SUMMARY One aspect of the present disclosure provides a circuit structure. The circuit structure includes a first metal line and a second metal line. The second metal line is disposed over the first metal line. At least one air gap is disposed between the first metal line and the second metal line. Another aspect of the present disclosure provides a circuit structure. The circuit structure includes a first metal line, a second metal line and a middle structure. The second metal line is disposed over the first metal line. The middle structure is interposed between the first metal line and the second metal line, and is configured to reduce a parasitic capacitance between the first metal line and the second metal line. The middle structure includes three different materials. Another aspect of the present disclosure provides a method of manufacturing a circuit structure. The method includes: providing an assembly structure including a first metal line; forming a second metal line over the first metal line; and forming at least one air gap between the first metal line and the second metal line. The foregoing has outlined rather broadly the features and technical advantages of the present disclosure so that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims when considered in connection with the Figures, where like reference numbers refer to similar elements throughout the Figures, and: FIG. 1 is a top view of a circuit structure in accordance with some embodiments of the present disclosure. FIG. 2 is a schematic cross-sectional view taken along line A1-A1 of FIG. 1. FIG. 3 is a schematic cross-sectional view taken along line B1-B1 of FIG. 1. FIG. 4 illustrates one or more stages of a method of manufacturing a circuit structure in accordance with some embodiments of the present disclosure. FIG. 5 is a schematic cross-sectional view taken along line A2-A2 of FIG. 4. FIG. 6 is a schematic cross-sectional view taken along line B2-B2 of FIG. 4. FIG. 7 illustrates one or more stages of a method of manufacturing a circuit structure in accordance with some embodiments of the present disclosure. FIG. 8 illustrates one or more stages of a method of manufacturing a circuit structure in accordance with some embodiments of the present disclosure. FIG. 9 is a schematic cross-sectional view taken along line A3-A3 of FIG. 8. FIG. 10 is a schematic cross-sectional view taken along line B3-B3 of FIG. 8. FIG. 11 illustrates one or more stages of a method of manufacturing a circuit structure in accordance with some embodiments of the present disclosure. FIG. 12 is a schematic cross-sectional view taken along line A4-A4 of FIG. 11. FIG. 13 is a schematic cross-sectional view taken along line B4-B4 of FIG. 11. FIG. 14 illustrates one or more stages of a method of manufacturing a circuit structure in accordance with some embodiments of the present disclosure. FIG. 15 is a schematic cross-sectional view taken along line A5-A5 of FIG. 14. FIG. 16 is a schematic cross-sectional view taken along line B5-B5 of FIG. 14. FIG. 17 illustrates one or more stages o