US-12628644-B2 - Semiconductor device and module

US12628644B2US 12628644 B2US12628644 B2US 12628644B2US-12628644-B2

Abstract

A semiconductor device having a semiconductor substrate with first and second main surfaces that face one another in a thickness direction, and a circuit layer disposed on the first main surface. The circuit layer has a first electrode layer on the semiconductor substrate, a dielectric layer on the first electrode layer, a second electrode layer on the dielectric layer, and first and second outer electrodes electrically connected to the first and second electrode layers, respectively. The semiconductor substrate has a first end-portion region in which the circuit layer is not provided on the semiconductor substrate and on the side of the first end surface. In the first end-portion region, a first exposed portion is provided that is exposed between the first main surface and the first end surface.

Inventors

Masatomi Harada
Takeshi Kagawa
Hiroshi Matsubara
Nobuyoshi ADACHI

Assignees

MURATA MANUFACTURING CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20220707
Priority Date: 20200120

Claims (20)

1 . A semiconductor device comprising: a semiconductor substrate having first and second main surfaces that face each other in a thickness direction, first and second end surfaces that face each other in a length direction orthogonal to the thickness direction, and first and second side surfaces that face each other in a width direction orthogonal to the thickness direction and the length direction; and a circuit layer disposed on the first main surface of the semiconductor substrate and including: a first electrode layer disposed above the first main surface of the semiconductor substrate, a dielectric layer disposed on the first electrode layer, a second electrode layer disposed on the dielectric layer, a first outer electrode electrically connected to the first electrode layer and extending away from the first main surface of the semiconductor substrate in the thickness direction, and a second outer electrode electrically connected to the second electrode layer and extending away from the first main surface of the semiconductor substrate in the thickness direction, wherein the semiconductor substrate is a continuous material that includes a first end-portion region where the circuit layer is not disposed on the semiconductor substrate and on a side of the first end surface that is an end surface of the semiconductor substrate on a second outer electrode side in the length direction, wherein, in the first end-portion region, a first exposed portion is disposed that is exposed between the first main surface and the first end surface, and wherein, in a section of the semiconductor substrate cut in parallel to the thickness direction and the length direction of the semiconductor substrate, when the first end-portion region is divided into two in the thickness direction by a division line dividing a portion of the semiconductor substrate having the first main surface on which the circuit layer is provided with a center in the thickness direction as a boundary, an area of a first region that is a region on a first main surface side is smaller than an area of a second region that is a region on a second main surface side.
2 . The semiconductor device according to claim 1 , wherein, in a section of the semiconductor substrate cut in parallel to the thickness direction and the length direction, the first exposed portion has a slope shape in which a distance from a virtual extension line of the first end surface to the first exposed portion in the length direction linearly changes from the first main surface toward the second main surface.
3 . The semiconductor device according to claim 2 , wherein, in a section of the semiconductor substrate cut in parallel to the thickness direction and the length direction, an angle between a virtual extension line of the first end surface and the first exposed portion is 4° or more and 36° or less.
4 . The semiconductor device according to claim 1 , wherein, in a section of the semiconductor substrate cut in parallel to the thickness direction and the length direction, the first exposed portion has a shape in which a distance from a virtual extension line of the first end surface to the first exposed portion in the length direction nonlinearly changes from the first main surface toward the second main surface.
5 . The semiconductor device according to claim 4 , wherein, when the first exposed portion is divided into two in the thickness direction at a portion at which the first exposed portion has a maximum thickness, a change of a distance, in a region on the first main surface side, from a virtual extension line of the first end surface to the first exposed portion in the length direction is smaller than a change of a distance, in a region on the second main surface side, from a virtual extension line of the first end surface to the first exposed portion in the length direction.
6 . The semiconductor device according to claim 1 , wherein, in a section of the semiconductor substrate cut in parallel to the thickness direction and the length direction, the first exposed portion has a shape having a region that is disposed on the first main surface side and in which a distance from a virtual extension line of the first end surface to the first exposed portion in the length direction does not change and a region that is disposed on the second main surface side and in which a distance from a virtual extension line of the first end surface to the first exposed portion in the length direction changes.
7 . The semiconductor device according to claim 1 , wherein, in a section of the semiconductor substrate cut in parallel to the thickness direction and the length direction, the first exposed portion has a shape having a region that is disposed on the first main surface side and in which a distance from a virtual extension line of the first end surface to the first exposed portion in the length direction linearly changes and a region that is disposed on the second main surface side and in which a distance from a virtual extension line of the first end surface to the first exposed portion in the length direction nonlinearly changes.
8 . The semiconductor device according to claim 1 , wherein, in a section of the semiconductor substrate cut in parallel to the thickness direction and the length direction, a ratio of a maximum thickness of the first exposed portion to a thickness of the semiconductor substrate is 30% or more and 70% or less.
9 . The semiconductor device according to claim 1 , wherein, in a section of the semiconductor substrate cut in parallel to the thickness direction and the length direction, a maximum length of a distance from a virtual extension line of the first end surface to the first exposed portion in the length direction is 5 μm or more and 20 μm or less.
10 . The semiconductor device according to claim 1 , wherein the semiconductor substrate has a second end-portion region in which the circuit layer is not provided on the first main surface and on a side of the second end surface that is an end surface of the semiconductor substrate on a first outer electrode side in the length direction, and wherein, in the second end-portion region, a second exposed portion is disposed that is exposed between the first main surface and the second end surface.
11 . The semiconductor device according to claim 10 , wherein, in a section of the semiconductor substrate cut in parallel to the thickness direction and the length direction, when the second end-portion region is divided into two in the thickness direction by a division line dividing a portion of the semiconductor substrate having the first main surface on which the circuit layer is provided with the center in the thickness direction as a boundary, an area of a third region that is a region on the first main surface side is smaller than an area of a fourth region that is a region on the second main surface side.
12 . The semiconductor device according to claim 11 , wherein, in a section of the semiconductor substrate cut in parallel to the thickness direction and the length direction, the first exposed portion and the second exposed portion each comprise a substantially linearly symmetrical shape to one another.
13 . The semiconductor device according to claim 1 , wherein the semiconductor substrate has, on a first side surface side, a first side-portion region in which the circuit layer is not provided on the first main surface, wherein, in the first side-portion region, a third exposed portion is disposed that is exposed between the first main surface and the first side surface, and wherein, in a section of the semiconductor substrate cut in parallel to the thickness direction and the width direction, when the first side-portion region is divided into two in the thickness direction by a division line dividing a portion of the semiconductor substrate having the first main surface on which the circuit layer is provided with the center in the thickness direction as a boundary, an area of a fifth region that is a region on the first main surface side is smaller than an area of a sixth region that is a region on the second main surface side.
14 . The semiconductor device according to claim 13 , wherein the semiconductor substrate has, on a second side surface side, a second side-portion region in which the circuit layer is not disposed on the first main surface, wherein, in the second side-portion region, a fourth exposed portion is disposed that is exposed between the first main surface and the second side surface, and wherein, in a section of the semiconductor substrate cut in parallel to the thickness direction and the width direction of the semiconductor substrate, when the second side-portion region is divided into two in the thickness direction by a division line dividing a portion of the semiconductor substrate having the first main surface on which the circuit layer is provided with the center in the thickness direction as a boundary, an area of a seventh region that is a region on the first main surface side is smaller than an area of an eighth region that is a region on the second main surface side.
15 . The semiconductor device according to claim 14 , wherein, in a section of the semiconductor substrate cut in parallel to the thickness direction and the width direction, the third exposed portion and the fourth exposed portion each comprise a substantially linearly symmetrical shape to one another.
16 . The semiconductor device according to claim 1 , further comprising an insulating layer disposed between the first main surface of the semiconductor substrate and the circuit layer, wherein the insulating layer does not extend on the first exposed portion, such that the first exposed portion is not covered.
17 . A module comprising: the semiconductor device according to claim 1 ; a first land electrically connected to the first outer electrode; and a second land electrically connected to the second outer electrode and that protrudes outward farther than the circuit layer.
18 . The module according to claim 17 , wherein an alternating current is configured to be applied between the first land and the second land.
19 . The module according to claim 17 , further comprising a mold resin that is disposed between the second land and the semiconductor substrate.
20 . The module according to claim 17 , wherein a total of a maximum thickness of the first exposed portion and a shortest distance from the semiconductor substrate to the second land is 35 μm or more and 235 μm or less.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation of PCT Application No. PCT/JP2021/001713, filed Jan. 19, 2021, which claims priority to Japanese Patent Application No. 2020-006847, filed Jan. 20, 2020, the entire contents of each of which are hereby incorporated in their entirety. TECHNICAL FIELD The present disclosure relates to a semiconductor device and a module. BACKGROUND In general, for capacitor elements used for a semiconductor integrated circuit, a Metal Insulator Metal (MIM) capacitor has been widely known. The MIM capacitor is a capacitor having a parallel-plate type structure in which a dielectric is held between a lower electrode and an upper electrode. For example, Japanese Unexamined Patent Application Publication No. 2008-252011 (hereinafter “Patent Document 1”) discloses a dielectric capacitor having a substrate on which one electrode, a dielectric layer, and the other electrode are layered in this order. In the dielectric capacitor, a first insulating layer covering the other electrode has a first cavity through which a portion of the upper surface of the other electrode is exposed, and a second insulating layer covering the first insulating layer has a second cavity through which a portion of the upper surface of the other electrode is exposed. The second cavity has an opening dimension larger than the opening dimension of the first cavity, and a surface of a recess is covered with an electrically conductive hydrogen barrier layer. Moreover, Japanese Unexamined Patent Application Publication No. 6-140275 (hereinafter “Patent Document 2”) discloses a capacitance element formed by a first metal film disposed on a surface of a support substrate, a dielectric thin film formed on the first metal film and having a high permittivity, and a second metal film disposed on the dielectric thin film. In the capacitance element, an end portion of the second metal film is positioned apart from the first metal film of the dielectric thin film. In Patent Document 2, it is further disclosed that the support substrate has a step portion for preventing stress concentration from being caused during heat treatment. However, when a voltage is applied after the dielectric capacitor described in Patent Document 1 has been mounted on a substrate and if the substrate is a conductor, there arises a problem that an electric field is produced between a land provided on the substrate and a base electrode. As a result, conductor loss is caused by the substrate itself imparting a resistance to the above-described electric field. In addition, Patent Document 2 discloses that the support substrate has the step portion for preventing stress concentration from being caused during heat treatment. However, regarding the capacitance element described in Patent Document 2, the underside of the support substrate and the second metal film are not on the same plane, and there is thus difficulty in surface mounting. SUMMARY OF THE INVENTION Accordingly, the exemplary aspects of the present disclosure provide a semiconductor device and a module that enable reduction in conductor loss caused by the resistance of a semiconductor substrate. In an exemplary aspect, a semiconductor device is provided that includes a semiconductor substrate having first and second main surfaces that face one another in a thickness direction, first and second end surfaces that face one another in a length direction orthogonal to the thickness direction, and first and second side surfaces that face one another in a width direction orthogonal to the thickness direction and the length direction. Moreover, the semiconductor device includes a circuit layer provided on the first main surface of the semiconductor substrate. The circuit layer has a first electrode layer provided on the semiconductor substrate side, a dielectric layer provided on the first electrode layer, a second electrode layer provided on the dielectric layer, a first outer electrode electrically connected to the first electrode layer and extended to a surface, of the circuit layer, on the opposite side to the semiconductor substrate, and a second outer electrode electrically connected to the second electrode layer and extended to a surface, of the circuit layer, on the opposite side to the semiconductor substrate. Moreover, the semiconductor substrate has a first end-portion region in which the circuit layer is not provided on the semiconductor substrate, on the side of the first end surface that is an end surface of the semiconductor substrate on the second outer electrode side in the length direction. In the first end-portion region, there is a first exposed portion that is a portion, other than the first main surface, of the semiconductor substrate exposed between the first main surface and the first end surface. In a section of the semiconductor substrate cut in parallel to the thickness direction and the length direction of the semiconductor substrate, when the f