US-12628645-B2 - Chip-scale package architectures containing a die back side metal and a solder thermal interface material

Abstract

An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10 −6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

Inventors

• Susmriti Das Mahapatra
• Malavarayan Sankarasubramanian
• Shenavia Howell
• John Harper
• Mitul Modi

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260512

Application Date

20240614

Claims (20)

1. 1 . An integrated circuit (IC) package structure, comprising: a die having a front side and a backside; a first material comprising a first metal over the backside, wherein the first material comprises a plurality of filler particles embedded within the first metal; and a second material comprising a second metal over the first material, wherein an interface between the first material and the second material comprises at least one intermetallic compound (IMC) of the first metal and the second metal, and wherein the second material has a first z-height and the first material has a second z-height less than the first z-height, wherein the first z-height is 500 microns or less, and the second z-height is 150 microns or less.
2. 2 . The IC package structure of claim 1 , wherein the first metal comprises copper, indium, gallium, aluminum, silver, or tin, or wherein the second metal comprises copper, zinc, aluminum, or nickel.
3. 3 . The IC package structure of claim 1 , wherein the filler particles comprise nickel, copper, silver, gold, cobalt, or aluminum.
4. 4 . The IC package structure of claim 1 , wherein the first material and the second material both cover substantially all of the backside of the die, or the first material is within a recess of the second material.
5. 5 . The IC package structure of claim 1 , wherein a second interface between the first material and a third material comprises a second IMC.
6. 6 . The IC package structure of claim 1 , wherein the first material has a thermal conductivity of not less than 40 W/mK and wherein the second material has a coefficient of thermal expansion (CTE) of not less than 18×10 −6 m/mK.
7. 7 . The IC package structure of claim 1 , further comprising: a package substrate coupled to the die; and a board coupled to the package substrate.
8. 8 . An integrated circuit (IC) package structure, comprising: a die having a front side and a backside; a first material comprising a first metal over the backside, wherein the first material has a thermal conductivity of not less than 40 W/mK; a second material comprising a second metal over the first material, wherein the second material has a coefficient of thermal expansion (CTE) of not less than 18×10 −6 m/mK; and a third material over the second material, wherein a first interface between the first material and the second material comprises a first intermetallic compound (IMC) of the first metal and the second metal, and wherein a second interface between the first material and the third material comprises a second IMC.
9. 9 . The IC package structure of claim 8 , wherein the first metal comprises copper, indium, gallium, aluminum, silver, or tin, or wherein the second metal comprises copper, zinc, aluminum, or nickel.
10. 10 . The IC package structure of claim 8 , wherein the first material comprises a plurality of filler particles embedded within the first metal.
11. 11 . The IC package structure of claim 8 , wherein the first material and the second material both cover substantially all of the backside of the die, or the first material is within a recess of the second material.
12. 12 . The IC package structure of claim 8 , wherein the second material has a first z-height and the first material has a second z-height less than the first z-height, the first z-height is 500 microns or less, and the second z-height is 150 microns or less.
13. 13 . The IC package structure of claim 8 , further comprising: a package substrate coupled to the die; and a board coupled to the package substrate.
14. 14 . An integrated circuit (IC) package structure, comprising: a die having a front side and a backside; a first material comprising a first metal over the backside, wherein the first material comprises a plurality of filler particles embedded within the first metal; a second material comprising a second metal over the first material; and a third material over the second material, wherein an interface between the first material and the second material comprises a first intermetallic compound (IMC) of the first metal and the second metal, and wherein a second interface between the first material and the third material comprises a second IMC.
15. 15 . The IC package structure of claim 14 , wherein the first metal comprises copper, indium, gallium, aluminum, silver, or tin, or wherein the second metal comprises copper, zinc, aluminum, or nickel.
16. 16 . The IC package structure of claim 14 , wherein the filler particles comprise nickel, copper, silver, gold, cobalt, or aluminum.
17. 17 . The IC package structure of claim 14 , wherein the first material and the second material both cover substantially all of the backside of the die, or the first material is within a recess of the second material.
18. 18 . The IC package structure of claim 14 , wherein the second material has a first z-height and the first material has a second z-height less than the first z-height.
19. 19 . The IC package structure of claim 18 , wherein the first z-height is 500 microns or less, and the second z-height is 150 microns or less.
20. 20 . The IC package structure of claim 14 , wherein the first material has a thermal conductivity of not less than 40 W/mK.

Description

CLAIM OF PRIORITY This application is a continuation of, and claims priority to, U.S. patent application Ser. No. 17/033,080, filed on Sep. 25, 2020 and titled “CHIP-SCALE PACKAGE ARCHITECTURES CONTAINING A DIE BACK SIDE METAL AND A SOLDER THERMAL INTERFACE MATERIAL,” which is incorporated by reference herein in its entirety. BACKGROUND Chip-scale package (CSP) architectures are evolving to reduce footprint and thickness for compliance with rising industry demand for ultra-small single-chip devices such as application-specific integrated circuits (ASICs), erasable programmable read-only memories (EPROMs), dedicated microprocessors and the like. To help achieve this goal, integrated circuit (IC) dies are made smaller and thinner to reduce overall package thickness, and package dimensions are reduced to house chips with a small margin of oversize. As the proportion of the CSP volume occupied by the chip itself grows, less space remains for package components such as integrated heat spreaders (IHS) for thermal management or for warpage-mitigating stiffeners. A mounting need exists to bring forward a new approach to thermal and warpage management in next-generation CSPs. BRIEF DESCRIPTION OF THE DRAWINGS The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only. FIG. 1A illustrates a cross-sectional view in the x-z plane of an IC package comprising a die backside metal (DBM) bonded to a die with a solder thermal interface material (STIM), according to some embodiments of the disclosure. FIG. 1B illustrates a cross-sectional view in the x-z plane of an IC package comprising a DBM bonded to a die with a STIM comprising a plurality of filler particles, according to some embodiments of the disclosure. FIG. 1C illustrates a plan view in the x-y plane of the package shown in FIGS. 1A and 1B, according to some embodiments of the disclosure. FIG. 2A illustrates a cross-sectional view in the x-z plane of a package comprising a DBM having a recess and STIM within the recess, according to some embodiments of the disclosure. FIG. 2B illustrates a plan view in the x-y plane of a package with the DBM removed to view the STIM, according to some embodiments of the disclosure. FIG. 2C illustrates a plan view in the x-y plane of a package with the DBM removed to show an alternate STIM embodiment, according to some embodiments of the disclosure. FIG. 3 illustrates a process flow chart summarizing an exemplary process flow for making a package comprising a DBM anchored to a die by a STIM for warpage and thermal management, according to some embodiments of the disclosure. FIG. 4 illustrates a flow chart summarizing an exemplary process to form a bilayer metal foil comprising a DBM material cladded by an STIM material by roller bonding, according to some embodiments of the disclosure. FIG. 5 illustrates a flow chart summarizing an exemplary process to form a bilayer metal foil comprising a DBM material cladded by an STIM material by an electroplating method, according to some embodiments of the disclosure. FIGS. 6A-6C illustrate cross-sectional views in the x-z plane of an exemplary process flow for forming bilayer foil comprising a DBM metal cladded by a STIM layer, according to some embodiments of the disclosure. FIGS. 7A and 7B illustrate cross-sectional views in the x-z plane of electrochemical process flows for formation of bilayer foil comprising a DBM layer and an electroplated STIM layer, according to some embodiments of the disclosure. FIG. 8A illustrates a cross-sectional view in the x-z plane of an exemplary process flow for forming the package illustrated in FIGS. 1A-1C, according to some embodiments of the disclosure. FIG. 8B illustrates a cross-sectional view in the x-z plane of an exemplary process flow for forming the package illustrated in FIGS. 2A-2C, according to some embodiments of the disclosure. FIG. 9A illustrates a cross-sectional view in the x-z plane of an exemplary implementation comprising the CSP package illustrated in FIGS. 1A-1C, according to some embodiments of the disclosure. FIG. 9B illustrates a cross-sectional view in the x-z plane of an exemplary implementation comprising a multi-die package, according to some embodiments of the disclosure. FIG. 10 illustrates a block diagram of a computing device as part of a system-on-chip (SoC) package in an implementation of IC packages comprising die backside metal (DBM) bonded to a die by a solder thermal interface material (STIM) according to some embodiments of the disclosure. DETAILED DESCRIPTION Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with th