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US-12628651-B2 - Electronic package, package substrate and manufacturing method thereof

US12628651B2US 12628651 B2US12628651 B2US 12628651B2US-12628651-B2

Abstract

An electronic package is provided, including a package substrate in which a circuit layer and a surface treatment layer are embedded in an insulating portion, and the surface treatment layer is coupled to a top surface of the circuit layer, but is not formed on a side surface of the circuit layer. Therefore, the circuit layer can maintain the original predetermined line spacing so that it is beneficial to be designed with fine line spacing/line width.

Inventors

  • Min-Yao CHEN
  • Andrew C. Chang

Assignees

  • AALTOSEMI INC.

Dates

Publication Date
20260512
Application Date
20230307
Priority Date
20220311

Claims (6)

  1. 1 . A package substrate, comprising: an insulating portion; a circuit layer embedded in the insulating portion; and a surface treatment layer embedded in the insulating portion and coupled to a top surface of the circuit layer, wherein the surface treatment layer is free from being formed on a side surface of the circuit layer, wherein a surface of the surface treatment layer is flush with a surface of the insulating portion, and wherein the surface treatment layer is made of nickel/gold (Ni/Au), nickel/palladium/gold (Ni/Pd/Au), or organic solderability preservatives (OSP).
  2. 2 . The package substrate of claim 1 , wherein the surface treatment layer is exposed from the insulating portion.
  3. 3 . An electronic package, comprising: the package substrate of claim 1 ; and an electronic component disposed on the insulating portion and electrically connected to the circuit layer.
  4. 4 . The electronic package of claim 3 , wherein the electronic component is electrically connected to the circuit layer by wire bonding.
  5. 5 . A method for manufacturing a package substrate, the method comprising: providing an insulating portion; forming a circuit layer embedded in the insulating portion; and forming a surface treatment layer on a top surface of the circuit layer, wherein the surface treatment layer is free from being on a side surface of the circuit layer, wherein a surface of the surface treatment layer is flush with a surface of the insulating portion, and wherein the surface treatment layer is made of nickel/gold (Ni/Au), nickel/palladium/gold (Ni/Pd/Au), or organic solderability preservatives (OSP).
  6. 6 . The method of claim 5 , wherein the surface treatment layer is exposed from the insulating portion.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is based upon and claims the right of priority to Taiwan Patent Application No. 111109058, having a filing date of Mar. 11, 2022, the disclosure of which is hereby incorporated by reference herein in its entirety for all purposes. BACKGROUND 1. Technical Field The present disclosure relates to a semiconductor package, and more particularly, to a package substrate with embedded traces and an electronic package made therefrom. 2. Description of Related Art with the vigorous development of the electronic industry, electronic products tend to be light, thin, short and small in form, while in terms of function, they tend to be high-performance, high-function, and high-speed research and development. Therefore, in order to meet the high integration and miniaturization requirements of semiconductor devices, package substrates with high-density and fine line spacing circuits are often used in the packaging process. As shown in FIG. 1, a conventional package substrate 1 includes a plurality of conductive traces 11 disposed on an outermost dielectric layer 10, and a metal layer 12 such as nickel/gold formed on the outer surface of the conductive traces 11, so that the conductive trace 11 and the metal layer 12 form a circuit structure 1a. However, in the conventional package substrate 1, the metal layer 12 is formed on a side surface 11c of each of the conductive traces 11, so that the metal layer 12 occupies the space between the conductive traces 11, causing each of the space widths between the circuit structures 1a (or the line spacing of the conductive traces 11) to be changed from the originally predetermined distance d1 between the side surfaces 11c of the conductive traces 11 to the distance d2 between the side surfaces 12c of the metal layers 12, which is reduced by about 10˜20 microns (that is, d1−d2=10˜20 microns). Thus, if the wiring is carried out at the originally predetermined distance d1, when the package substrate 1 is wired in the subsequent process, the adjacent conductive traces 11 are likely to be in contact with each other because the distance d2 between the metal layers 12 is too close, resulting in a short circuit. Moreover, since the metal layer 12 occupies the space between the conductive traces 11 (so that making the surface shape present a circular arc), the bonding contacts on the adjacent conductive traces 11 are easily shifted, resulting in the wire bonding not being sticky-solid. Thus, when designing the circuit structure 1a, it is necessary to increase the distance d1 between the side surfaces 11c of the conductive traces 11 to avoid the problem of short circuit, but it also makes the package substrate 1 incapable of development of in the direction of fine spacing/fine lines, and thus it is difficult for the conventional package substrate 1 to meet the requirements for high-density contacts of semiconductor chips. Therefore, how to overcome various problems of the above-mentioned prior art has become an urgent problem to be solved at present. SUMMARY In view of the various deficiencies of the prior art mentioned above, the present disclosure provides a package substrate, comprising an insulating portion; a circuit layer embedded in the insulating portion; and a surface treatment layer embedded in the insulating portion and coupled to a top surface of the circuit layer, wherein the surface treatment layer is free from being formed on a side surface of the circuit layer. The present disclosure also provides a method for manufacturing a package substrate, the method comprising: providing an insulating portion; forming a circuit layer embedded in the insulating portion; and forming a surface treatment layer on a top surface of the circuit layer, wherein the surface treatment layer is free from being formed on a side surface of the circuit layer. In the aforementioned package substrate and its manufacturing method, a surface of the surface treatment layer is flush with a surface of the insulating portion so that the surface treatment layer is exposed from the insulating portion. In the aforementioned package substrate and its manufacturing method, the surface treatment layer is made of a conductive material. The present disclosure further provides an electronic package, comprising: the package substrate mentioned above; and an electronic component disposed on the insulating portion and electrically connected to the circuit layer. In the aforementioned electronic package, the electronic component is electrically connected to the circuit layer by wire bonding. As can be seen from the above, in the electronic package and its package substrate of the present disclosure, the surface treatment layer is not formed on the side surface of the circuit layer so that the surface treatment layer does not occupy the side space of the circuit layer. Therefore, the side space of the circuit layer can maintain the originally predetermined line