US-12628652-B2 - Supporting sealant layer structure for stacked die application

US12628652B2US 12628652 B2US12628652 B2US 12628652B2US-12628652-B2

Abstract

Some implementations described herein provide techniques and apparatuses for forming a stacked die product including two or more integrated circuit dies. A bond interface between two integrated circuit dies that are included in the stacked die product includes a layered structure. As part of the layered structure, respective layers of a sealant material are directly on co-facing surfaces of the two integrated circuit dies. The layered structure further includes one or more bonding layers between the respective layers of the sealant material that are directly on the co-facing surfaces of the two integrated circuit dies. The layered structure may reduce lateral stresses throughout the bond interface to reduce a likelihood of warpage of the two integrated circuit dies.

Inventors

Che Wei Yang
Kuo-Ming Wu
Sheng-Chau Chen
Cheng-Yuan Tsai
HAU-YI HSIAO
Chung-Yi Yu

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260512
Application Date: 20230410

Claims (20)

1 . A method, comprising: dispensing a layer of a siloxane-based compound across a first semiconductor substrate; curing the layer of the siloxane-based compound; forming, after curing the layer of the siloxane-based compound, a first bonding layer over the layer of the siloxane-based compound; and joining the first bonding layer to a second bonding layer that is associated with a second semiconductor substrate.
2 . The method of claim 1 , further comprising: forming a dielectric layer over the layer of the siloxane-based compound prior to forming the first bonding layer over the layer of the siloxane-based compound.
3 . The method of claim 1 , further comprising: forming a first set of interconnect structures through the first bonding layer and the layer of the siloxane-based compound; and joining the first set of interconnect structures to a second set of interconnect structures associated with the second semiconductor substrate.
4 . The method of claim 1 , further comprising: forming one or more stress-relief cavities in the first semiconductor substrate prior to dispensing the layer of the siloxane-based compound across the first semiconductor substrate.
5 . The method of claim 4 , further comprising: filling the one or more stress-relief cavities with the layer of the siloxane-based compound.
6 . A method, comprising: forming a first layer of a silazane-based compound, to a thickness that is included in a range of approximately one micron to approximately twenty microns, over a portion of a first integrated circuit die; forming a first dielectric layer over the first layer of the silazane-based compound; forming a second layer of the silazane-based compound over a portion of a second integrated circuit die; forming a second dielectric layer over the second layer of the silazane-based compound; and joining the first dielectric layer and the second dielectric layer.
7 . The method of claim 6 , wherein forming the first layer of the silazane-based compound over the portion of the first integrated circuit die comprises: forming the first layer of the silazane-based compound over beveled edges only of the first integrated circuit die.
8 . The method of claim 6 , wherein forming the first layer of the silazane-based compound over the portion of the first integrated circuit die comprises: forming the first layer of the silazane-based compound over an entire width of the first integrated circuit die.
9 . The method of claim 6 , wherein joining the first dielectric layer and the second dielectric layer comprises: joining the first dielectric layer and the second dielectric layer using a eutectic bonding process.
10 . A device, comprising: a first bonding layer; a first layer of a siloxane-based compound or a silazane-based compound between the first bonding layer and a first integrated circuitry, wherein the first integrated circuitry is associated with a first integrated circuit die; a second bonding layer joined with the first bonding layer; a second layer of the siloxane-based compound or the silazane-based compound between the second bonding layer and a second integrated circuitry, wherein the second integrated circuitry is associated with a second integrated circuit die; a first set of connection structures interspersed through the first bonding layer and the first layer of the siloxane-based compound or the silazane-based compound; and a second set of connection structures interspersed through the second bonding layer and the first layer of the siloxane-based compound or the silazane-based compound, wherein the second set of connection structures joins with the first set of connection structures.
11 . The device of claim 10 , further comprising: one or more stress-relief structures within the first integrated circuitry.
12 . The device of claim 10 , wherein the first layer of the siloxane-based compound or the silazane-based compound and the second layer of the siloxane-based compound or the silazane-based compound comprise: composite filler particulates.
13 . The device of claim 10 , further comprising: a beveled region, wherein the first layer of the siloxane-based compound or the silazane-based compound and the second layer of the siloxane-based compound or the silazane-based compound are directly joined within the beveled region.
14 . The device of claim 10 , further comprising: an interposer, and wherein a stacked die structure including the first bonding layer, the first layer of the siloxane-based compound or the silazane-based compound, the second bonding layer, and the second layer of the siloxane-based compound or the silazane-based compound is attached to the interposer.
15 . The device of claim 10 further comprising: a beveled region, wherein a bond interface structure is located between the first layer of the siloxane-based compound or the silazane-based compound, and the second layer of the siloxane-based compound or the silazane-based compound, within the beveled region.
16 . The device of claim 15 , wherein the bond interface structure comprises: the first bonding layer joined directly with the second bonding layer.
17 . The device of claim 16 , further comprising: a dielectric layer between the first bonding layer and the first layer of the siloxane-based compound or the silazane-based compound within the beveled region.
18 . The method of claim 1 , wherein the layer of the siloxane-based compound comprises composite filler particulates selected from silicon carbide (SiC), aluminum dioxide (Al 2 O 3 ), zirconium tungsten phosphate (Zr 2 WP 2 O 12 ), silica (SiO 2 ), or ceramic particulates.
19 . The method of claim 6 , wherein the first dielectric layer comprises a material selected from silicon dioxide (SiO 2 ), silicon oxycarbide (SiOC), aluminum dioxide (Al 2 O 3 ), undoped silicon glass, or phosphosilicate glass.
20 . The device of claim 10 , wherein at least one of the first layer of the siloxane-based compound or the silazane-based compound or the second layer of the siloxane-based compound or the silazane-based compound has a thickness in a range of approximately one micron to approximately twenty microns.

Description

BACKGROUND A three dimensional integrated circuit (3DIC) assembly may include two or more integrated circuit (IC) dies that are stacked vertically and bonded along a bond line. The 3DIC assembly may be formed by stacking two or more semiconductor substrates including the two or more IC dies using a wafer bonding operation such as a Wafer-on-Wafer (WoW) bonding operation. After the bonding operation, the 3DIC assembly including the two or more IC dies may be diced from the stack of two or more semiconductor substrates and encapsulated in a semiconductor die package. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a diagram of an example environment in which systems and/or methods described herein may be implemented. FIG. 2 is a diagram of an example implementation of formation of a stacked die product described herein. FIG. 3 is a diagram of an implementation of an example semiconductor die package including a stacked die product described herein. FIGS. 4A-4C are diagrams of example implementations of example semiconductor substrate based supporting layered structures including sealant layers described herein. FIGS. 5A-5C are diagrams of example implementations of example semiconductor die based supporting layered structures including a sealant layer described herein. FIG. 6 is a diagram of an example implementation of an example stress-relief structure described herein. FIGS. 7A-7F are diagrams of an example implementation of forming a layered structure including a sealant layer described herein. FIG. 8 is a diagram of example components of one or more devices of FIG. 1 described herein. FIGS. 9 and 10 are flowcharts of example processes associated with forming a supporting sealant layer for a stacked die application. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In some cases, a stacked die product, such as a wafer-on-wafer (WoW) product, may include a single material (e.g., a silicon oxynitride (SiON) material) that is shared along a bond interface between co-facing surfaces of two integrated circuit dies that are joined together. In some cases, lateral stresses present throughout such a bond interface may cause a warpage of the stacked die product. Additionally, such a bond interface may possess a rigidity characteristic that fails to sufficiently dampen vibrations and/or reduce stresses along the bond interface during an operation that thins the stacked die product. In such cases, the bond interface may crack or peel during the thinning operation, cause the two integrated circuit dies to separate, and render the stacked die product to be non-functional. Further, and to mitigate such warpage, cracking, and/or peeling, one or more additional processing operations may be implemented, such as a trimming operation along a perimeter of two or more semiconductor substrates that are joined as part of forming the stacked die product. Some implementations described herein provide techniques and apparatuses for forming a stacked die product including two or more integrated circuit dies. A bond interface between two inte