US-12628653-B2 - Semiconductor device and method of manufacture

Abstract

A device includes a redistribution structure, including conductive features; dielectric layers; and an internal support within a first dielectric layer of the dielectric layers, wherein the internal support is free of passive and active devices; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent the first interconnect structure, wherein the internal support laterally overlaps both the first interconnect structure and the second interconnect structure.

Inventors

• Jiun Yi Wu
• Chen-Hua Yu

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date

20260512

Application Date

20240701

Claims (20)

1. 1 . A method comprising: bonding a first core substrate and a second core substrate to a first side of a first redistribution structure; forming a support structure within the first redistribution structure, wherein the support structure is physically separated from conductive elements of the first redistribution structure, wherein the support structure overlaps the first core substrate and the second core substrate; and bonding an integrated circuit package to a second side of the first redistribution structure.
2. 2 . The method of claim 1 , further comprising depositing a molding material between the first core substrate and the first side of the first redistribution structure.
3. 3 . The method of claim 1 , wherein the support structure overlaps two integrated circuit dies of the integrated circuit package.
4. 4 . The method of claim 1 , wherein the first core substrate is bonded to the first redistribution structure by first conductive connectors, wherein the integrated circuit package is bonded to the first redistribution structure by second conductive connectors that have a smaller width than the first conductive connectors.
5. 5 . The method of claim 1 , wherein the support structure comprises a ceramic material.
6. 6 . The method of claim 1 , wherein a length of the support structure is larger than a length of the first core substrate.
7. 7 . The method of claim 1 , further comprising bonding a third core substrate to the first side of the first redistribution structure, wherein the support structure overlaps the third core substrate.
8. 8 . The method of claim 1 , wherein forming the support structure within the first redistribution structure comprises depositing a dielectric layer on a top surface of the support structure.
9. 9 . A method comprising: forming a redistribution structure, wherein the redistribution structure comprises: a plurality of metallization patterns; a plurality of dielectric layers; and a plurality of insulating support structures, wherein the insulating support structures are respectively sandwiched between two of the dielectric layers; attaching a plurality of interconnect substrates to a first side of the redistribution structure; wherein a first insulating support structure overlaps at least two interconnect substrates; and attaching a package to a second side of the redistribution structure, wherein the package comprises a plurality of dies, wherein the first insulating support structure overlaps at least two dies.
10. 10 . The method of claim 9 , wherein the at least two interconnect substrates are laterally adjacent.
11. 11 . The method of claim 9 , further comprising depositing a molding material between the at least two interconnect substrates.
12. 12 . The method of claim 9 , wherein a second insulating support structure is closer to the package than the first insulating support structure.
13. 13 . The method of claim 9 , wherein a portion of a metallization pattern extends between two of the insulating support structures.
14. 14 . The method of claim 9 , wherein two of the insulating support structures have different widths.
15. 15 . The method of claim 9 , wherein two of the insulating support structures overlap the same two interconnect substrates.
16. 16 . A method comprising: forming first layers of a redistribution structure; attaching a dummy die to the first layers of the redistribution structure; forming second layers of the redistribution structure on the dummy die and the first layers of the redistribution structure, wherein the dummy die is physically separated from conductive elements of the redistribution structure; bonding interconnect structures to the second layers of the redistribution structure, wherein the dummy die overlaps at least two of the interconnect structures; and bonding semiconductor dies to the first layers of the redistribution structure.
17. 17 . The method of claim 16 , wherein attaching the dummy die comprises depositing an adhesive on the dummy die.
18. 18 . The method of claim 16 , wherein the first layers of the redistribution structure comprise first dielectric layers and the second layers of the redistribution structure comprise second dielectric layers that are a different dielectric material than the first dielectric layers.
19. 19 . The method of claim 16 , wherein bonding the semiconductor dies to the second layers of the redistribution structure comprises bonding the semiconductor dies to a routing structure and then bonding the routing structure to the second layers of the redistribution structure.
20. 20 . The method of claim 16 , wherein the dummy die comprises a semiconductor material.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application is a continuation of U.S. patent application Ser. No. 18/359,684, entitled “Semiconductor Device and Method of Manufacture,” and filed on Jul. 26, 2023, which is a continuation of U.S. patent application Ser. No. 17/815,338, entitled “Semiconductor Device and Method of Manufacture,” and filed on Jul. 27, 2022, now U.S. Pat. No. 11,894,318 issued Feb. 6, 2024, which is a divisional application of U.S. patent application Ser. No. 17/097,206, entitled “Semiconductor Device and Method of Manufacture,” and filed Nov. 13, 2020, now U.S. Pat. No. 11,784,140 issued Oct. 10, 2023, which claims the benefit of U.S. Provisional Application No. 63/031,679, filed on May 29, 2020, which applications are hereby incorporated herein by reference in its entirety. BACKGROUND The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components, hence more functions, to be integrated into a given area. Integrated circuits with high functionality require many input/output pads. Yet, small packages may be desired for applications where miniaturization is important. As the demand for shrinking electronic devices has grown, a need for smaller and more creative packaging techniques of semiconductor dies has emerged. An example of such packaging systems is Package-on-Package (POP) technology. In a POP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology generally enables production of semiconductor devices with enhanced functionalities and small footprints on a printed circuit board (PCB). BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a cross-sectional view of an intermediate step of forming first redistribution layers of a redistribution structure, in accordance with some embodiments. FIG. 2A illustrates a plan view of an intermediate step of forming first redistribution layers of a redistribution structure, in accordance with some embodiments. FIGS. 2B and 2C illustrate cross-sectional views of intermediate steps of forming structures on carrier substrates, in accordance with some embodiments. FIGS. 3, 4, and 5 illustrate cross-sectional views of intermediate steps of forming first redistribution layers of a redistribution structure, in accordance with some embodiments. FIG. 6 illustrates a cross-sectional view of an intermediate step of forming an internal support in a redistribution structure, in accordance with some embodiments. FIG. 7 illustrates a plan-sectional view of an intermediate step of forming an internal support in a redistribution structure, in accordance with some embodiments. FIGS. 8, 9, and 10 illustrate cross-sectional views of intermediate steps of forming second redistribution layers of a redistribution structure, in accordance with some embodiments. FIG. 11 illustrates a cross-sectional view of an interconnect structure, in accordance with some embodiments. FIGS. 12, 13, and 14 illustrate cross-sectional views of intermediate steps of bonding interconnect structures to a redistribution structure, in accordance with some embodiments. FIG. 15 illustrates a plan view of an intermediate step of bonding interconnect structures to a redistribution structure, in accordance with some embodiments. FIGS. 16, 17, and 18 illustrate cross-sectional views of intermediate steps of forming a package structure, in accordance with some embodiments. FIGS. 19, 20, 21, 22, 23, and 24 illustrate cross-sectional views of intermediate steps of forming first redistribution layers and second redistribution layers of a redistribution structure, in accordance with some embodiments. FIGS. 25 and 26 illustrate cross-sectional views of intermediate steps of forming a package structure, in accordance with some embodiments. FIGS. 27, 28, 29, 30A, 30B, and 30C illustrate cross-sectional views and plan views of package structures having internal supports, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which