US-12628654-B2 - Chip package with electromagnetic interference shielding layer and method of manufacturing the same

US12628654B2US 12628654 B2US12628654 B2US 12628654B2US-12628654-B2

Abstract

A chip package with electromagnetic interference (EMI) shielding layer and a method of manufacturing the same are provided. The chip package includes a chip, a redistribution layer (RDL), an insulating layer, and an electromagnetic interference (EMI) shielding layer. A peripheral wall is formed around at least one first opening of the insulating layer for enclosing the first opening and a flat portion is disposed around the peripheral wall while a level of the flat portion is lower than a level of the peripheral wall. The flat portion of the insulating layer is covered with the EMI shielding layer which is isolated and electrically insulated from a pad in the first opening by the peripheral wall of the insulating layer. Thereby problems of the chip including fast increase in temperature and electromagnetic interference can be solved effectively.

Inventors

Hong-Chi Yu
Chun-Jung Lin
Ruei-Ting Gu

Assignees

WALTON ADVANCED ENGINEERING, INC.

Dates

Publication Date: 20260512
Application Date: 20230908
Priority Date: 20221026

Claims (12)

1 . A chip package with at least one electromagnetic interference (EMI) shielding layer comprising: a chip provided with a surface on which at least one die pad and at least one chip protective layer are disposed; wherein the chip is formed by cutting a wafer; a redistribution layer (RDL) arranged at a surface of the at least one chip protective layer of the chip and provided with at least one conductive circuit which is electrically connected with the at least one die pad of the chip; the at least one conductive circuit is provided with at least one pad which is exposed on a surface of the RDL for electrically connected with outside; an insulating layer covering and disposed on the surface of the RDL completely and provided with at least one first opening for allowing the at least one pad of the conductive circuit to be exposed; wherein a peripheral wall is formed around the at least one first opening of the insulating layer for enclosing the at least one first opening and a flat portion is disposed around the peripheral wall; wherein a level of the flat portion is lower than a level of the peripheral wall; and an EMI shielding layer made of metal and covering the flat portion of the insulating layer for preventing the at least one conductive circuit and the chip from an electromagnetic interference; wherein the EMI shielding layer is isolated and electrically insulated from the at least one pad by the peripheral wall of the insulating layer.
2 . The chip package as claimed in claim 1 , wherein the EMI shielding layer is made of silver (Ag) adhesive.
3 . The chip package as claimed in claim 1 , wherein a level of the EMI shielding layer is not higher than a level of the peripheral wall of the insulating layer.
4 . The chip package as claimed in claim 1 , wherein the at least one first opening of the insulating layer is further provided with at least one solder ball so that the at least one pad of the conductive circuit is able to be electrically connected with the outside by the at least one solder ball; wherein the at least one solder ball is isolated and electrically insulated from the EMI shielding layer by the peripheral wall of the insulating layer.
5 . The chip package as claimed in claim 1 , wherein a surface of the EMI shielding layer is further provided with at least one outer protective layer.
6 . The chip package as claimed in claim 1 , wherein the at least one outer protective layer is made of metal including nickel (Ni) and gold (Au).
7 . The chip package as claimed in claim 1 , wherein the RDL further includes at least one first dielectric layer and at least one second dielectric layer; wherein the at least one first dielectric layer is covering a surface of the at least one chip protective layer of the chip and provided with at least one first groove for allowing the at least one die pad to be exposed by the at least one first groove; wherein the at least one second dielectric layer is covering a surface of the at least one first dielectric layer and provided with at least one second groove which is communicating with the at least one first groove of the at least one first dielectric layer; wherein the at least one conductive circuit is further formed by a metal paste being filled into the at least one first groove and the at least one second groove smoothly and fully; thereby the at least one die pad is electrically connected with the at least one conductive circuit.
8 . The chip package as claimed in claim 1 , wherein the at least one conductive circuit is made of silver (Ag) adhesive.
9 . The chip package as claimed in claim 1 , wherein the at least one conductive circuit further includes a projecting block which is made of metal including nickel (Ni) and gold (Au).
10 . A method of manufacturing a chip package with at least one electromagnetic interference (EMI) shielding layer comprising the steps of: Step S 1 : providing a wafer on which a plurality of chips is disposed to form an array and each of the plurality of chips includes a surface on which at least one die pad and at least one chip protective layer are disposed; wherein a cut groove is formed between two adjacent chips of the wafer for separating the plurality of chips; Step S 2 : covering a surface of the at least one chip protective layer of the chip with a redistribution layer (RDL) and the RDL having at least one conductive circuit which is electrically connected with the at least one die pad of the chip while the at least one conductive circuit is provided with at least one pad which is exposed on a surface of the RDL for electrically connected with outside; Step S 3 : covering a surface of the RDL with an insulating layer completely and the insulating layer is provided with at least one first opening for allowing the at least one pad of the at least one conductive circuit to be exposed by the at least one first opening; Step S 4 : forming a peripheral wall around the at least one first opening of the insulating layer for enclosing the at least one first opening and forming a flat portion around the peripheral wall of the insulating layer; wherein a level of the flat portion is lower than a level of the peripheral wall; Step S 5 : covering the flat portion of the insulating layer with an electromagnetic interference (EMI) shielding layer and the EMI shielding layer is made of metal; wherein the EMI shielding layer is isolated and electrically insulated from the at least one pad by the peripheral wall of the insulating layer; and Step S 6 : cutting along the cut groove of the wafer for separating the plurality of chips on the wafer to form a plurality of chip packages.
11 . The method as claimed in claim 10 , wherein the surface of the at least one chip protective layer of the chip is covered with at least one first dielectric layer and at least one first groove is formed on the at least one first dielectric layer so that the at least one die pad is exposed by the at least one first groove; wherein a surface of the at least one first dielectric layer is covered with at least one second dielectric layer and at least one second groove is formed on the at least one second dielectric layer while the at least one second groove is communicating with the at least one first groove of the at least one first dielectric layer; wherein a metal paste is filled into the at least one first groove and the at least one second groove and a level of the metal paste is higher than a surface of the at least one second dielectric layer; wherein the metal paste with the level higher than a surface of the at least one second dielectric layer is ground to expose the surface of the at least one second dielectric layer and thus a surface of the metal paste is at the same level as the surface of the at least one second dielectric layer to form the at least one conductive circuit; wherein the at least one conductive circuit, the at least one first dielectric layer, and the at least one second dielectric layer form the RDL.
12 . The method as claimed in claim 10 , wherein in the step S 5 , first the flat portion of the of the insulating layer is fully filled with a metal paste and a level of the metal paste is higher than a level of the peripheral wall; wherein the metal paste with the level higher than the peripheral wall is ground to expose a horizontal surface of the peripheral wall; thereby a horizontal surface of the metal paste is flush with the horizontal surface of the peripheral wall to form the EMI shielding layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This non-provisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No(s). 111140642 filed in Taiwan, R.O.C. on Oct. 26, 2022, the entire contents of which are hereby incorporated by reference. BACKGROUND OF THE INVENTION The present invention relates to a chip package and a method of manufacturing the same, especially to a chip package with electromagnetic interference (EMI) shielding layer and a method of manufacturing the same. As the use time increases, temperature of chips in electronic products is getting higher. This leads to short circuit, failure, or even damages of the electronics and thus product reliability is further reduced. Moreover, chips in electronic products are susceptible to electromagnetic Interference and thus product reliability is lowered. SUMMARY OF THE INVENTION Therefore, it is a primary object of the present invention to provide a chip package with electromagnetic interference (EMI) shielding layer, which includes a chip, a redistribution layer (RDL), an insulating layer, and an electromagnetic interference (EMI) shielding layer. A peripheral wall is formed around at least one first opening of the insulating layer for enclosing the first opening and a flat portion is disposed around the peripheral wall while a level of the flat portion is lower than a level of the peripheral wall. The flat portion of the insulating layer is covered with the EMI shielding layer for preventing the chip from electromagnetic interference. The EMI shielding layer is isolated and electrically insulated from the pad in the first opening by the peripheral wall of the insulating layer. Thereby problems of the chip including easy increase in temperature and electromagnetic interference can be solved effectively. In order to achieve the above object, a chip package with electromagnetic interference (EMI) shielding layer according to the present invention includes a chip, a redistribution layer (RDL), an insulating layer, and an electromagnetic interference (EMI) shielding layer. The chip is provided with a surface on which at least one die pad and at least one chip protective layer are disposed. The chip is formed by cutting a wafer. The RDL is arranged at a surface of the chip protective layer of the chip and provided with at least one conductive circuit which is electrically connected with the die pad of the chip. The conductive circuit is provided with at least one pad which is exposed on a surface of the RDL for electrically connected with the outside. The surface of the RDL is covered with the insulating layer completely and the insulating layer is provided with at least one first opening for allowing the pad of the conductive circuit to be exposed by the first opening. A peripheral wall is formed around the first opening of the insulating layer for enclosing the first opening and a flat portion is disposed around the peripheral wall while a level of the flat portion is lower than a level of the peripheral wall. The EMI shielding layer is made of metal and covering the flat portion of the insulating layer for preventing the conductive circuit and the chip from electromagnetic interference. The EMI shielding layer is isolated and electrically insulated from the pad by the peripheral wall of the insulating layer. Preferably, the RDL further includes at least one first dielectric layer and at least one second dielectric layer. The first dielectric layer is covering a surface of the chip protective layer of the chip and provided with at least one first groove for allowing the die pad to be exposed by the first groove. The second dielectric layer is covering a surface of the first dielectric layer and provided with at least one second groove which is communicating with the first groove of the first dielectric layer. The conductive circuit is further formed by a metal paste being filled into the first groove and the second groove smoothly and fully. Thereby the die pad is electrically connected with the conductive circuit. It is another object of the present invention to provide a method of manufacturing a chip package with electromagnetic interference (EMI) shielding layer having the following steps. Step S1: providing a wafer on which a plurality of chips is disposed to form an array and each of the chips includes a surface on which at least one die pad and at least one chip protective layer are disposed. A cut groove is formed between the two adjacent chips of the wafer for separating the chips. Step S2: covering a surface of the chip protective layer of the chip with at least one redistribution layer (RDL) and the RDL having at least one conductive circuit which is electrically connected with the die pad of the chip while the conductive circuit is provided with at least one pad which is exposed on a surface of the RDL for electrically connected with the outside. Step S3: covering a surface of the RDL with an insulating layer completely