US-12628659-B2 - Semiconductor package

Abstract

A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.

Inventors

• Sang Cheon Park
• Young Min Lee
• Dae-woo Kim
• Hyuek Jae Lee

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20230817

Priority Date

20200903

Claims (20)

1. 1 . A semiconductor package comprising: a first semiconductor chip; a first alignment pad provided on an upper surface of the first semiconductor chip; a first bonding pad spaced apart from the first alignment pad in a first direction on the upper surface of the first semiconductor chip; a second alignment pad including an opening part which is provided on an upper surface of the first alignment pad and an alignment part which does not overlap the first alignment pad in a second direction different from the first direction; a second bonding pad provided on an upper surface of the first bonding pad, a lower surface of the second bonding pad being in contact with the upper surface of the first bonding pad, the second bonding pad spaced apart from the second alignment pad in the first direction; and a second semiconductor chip provided on an upper surface of the second alignment pad and an upper surface of the second bonding pad, wherein a lower surface of the first bonding pad is coplanar with a lower surface of the first alignment pad.
2. 2 . The semiconductor package of claim 1 , wherein the first semiconductor chip includes a first wiring pattern which is electrically connected to the first bonding pad, and wherein the first wiring pattern does not overlap the first alignment pad and the second alignment pad in the second direction.
3. 3 . The semiconductor package of claim 1 , wherein the second semiconductor chip includes a second wiring pattern which is electrically connected to the second bonding pad, and wherein the second wiring pattern does not overlap the first alignment pad and the second alignment pad in the second direction.
4. 4 . The semiconductor package of claim 1 , wherein the second alignment pad includes a first part having a box shape including an inner wall and an outer wall of a quadrangular shape, and a second part having a cross shape provided inside the inner wall of the first part, and wherein the first alignment pad has a quadrangular shape and is provided in a space defined by the first part and the second part of the second alignment pad.
5. 5 . The semiconductor package of claim 1 , wherein the second alignment pad includes the same material as the second bonding pad.
6. 6 . The semiconductor package of claim 1 , wherein a thickness of the second alignment pad in the second direction is the same as a thickness of the second bonding pad in the second direction.
7. 7 . The semiconductor package of claim 1 , wherein the second alignment pad includes the same material as the first alignment pad, and wherein a thickness of the second alignment pad in the second direction is the same as a thickness of the first alignment pad in the second direction.
8. 8 . The semiconductor package of claim 1 , wherein a thickness of the first alignment pad in the second direction is smaller than a thickness of the first bonding pad in the second direction.
9. 9 . The semiconductor package of claim 1 , wherein a thickness of the second alignment pad in the second direction is smaller than a thickness of the second bonding pad in the second direction.
10. 10 . The semiconductor package of claim 1 , further comprising: a first passivation layer which is provided on the upper surface of the first semiconductor chip and surrounds side faces of the first bonding pad and side faces of the first alignment pad; and a second passivation layer which is provided on an upper surface of the first passivation layer and surrounds side faces of the second bonding pad and side faces of the second alignment pad.
11. 11 . A semiconductor package comprising: a first semiconductor chip; a first alignment pad provided on an upper surface of the first semiconductor chip; a first bonding pad spaced apart from the first alignment pad in a first direction on the upper surface of the first semiconductor chip; a first passivation layer provided on the upper surface of the first semiconductor chip, the first passivation layer surrounding side faces of the first bonding pad and side faces of the first alignment pad; a second alignment pad including an opening part provided on an upper surface of the first alignment pad; a second bonding pad provided on an upper surface of the first bonding pad, a lower surface of the second bonding pad being in contact with the upper surface of the first bonding pad, the second bonding pad spaced apart from the second alignment pad in the first direction; a second passivation layer provided on an upper surface of the first passivation layer, the second passivation layer surrounding side faces of the second bonding pad and side faces of the second alignment pad; and a second semiconductor chip provided on an upper surface of the second alignment pad and an upper surface of the second bonding pad, wherein the second alignment pad includes an alignment part and the opening part which penetrates the alignment part and exposes at least a part of the second semiconductor chip, wherein the first alignment pad overlaps the opening part in a second direction different from the first direction and does not overlap the alignment part in the second direction, and wherein a lower surface of the first bonding pad is coplanar with a lower surface of the first alignment pad.
12. 12 . The semiconductor package of claim 11 , wherein the upper surface of the first alignment pad is in contact with a lower surface of the second passivation layer, and wherein a lower surface of the second alignment pad is in contact with the upper surface of the first passivation layer.
13. 13 . The semiconductor package of claim 11 , wherein the first semiconductor chip includes a first wiring pattern which is electrically connected to the first bonding pad, and wherein the first wiring pattern does not overlap the first alignment pad and the second alignment pad in the second direction.
14. 14 . The semiconductor package of claim 11 , wherein the second semiconductor chip includes a second wiring pattern which is electrically connected to the second bonding pad, and wherein the second wiring pattern does not overlap the first alignment pad and the second alignment pad in the second direction.
15. 15 . The semiconductor package of claim 11 , wherein a thickness of the first alignment pad in the second direction is smaller than a thickness of the first bonding pad in the second direction.
16. 16 . The semiconductor package of claim 11 , wherein a thickness of the second alignment pad in the second direction is smaller than a thickness of the second bonding pad in the second direction.
17. 17 . A semiconductor package comprising: a first semiconductor chip including a first wiring pattern; a first alignment pad provided on an upper surface of the first semiconductor chip, the first alignment pad electrically insulated from the first wiring pattern; a first bonding pad spaced apart from the first alignment pad in a first direction on the upper surface of the first semiconductor chip, the first bonding pad electrically connected to the first wiring pattern; a second alignment pad including an opening part which is provided on an upper surface of the first alignment pad and an alignment part which does not overlap the first alignment pad in a second direction different from the first direction, the second alignment pad electrically insulated from the first alignment pad and the first wiring pattern; and a second bonding pad provided on an upper surface of the first bonding pad, the second bonding pad spaced apart from the second alignment pad in the first direction, wherein the second bonding pad is electrically connected to the first bonding pad, and the second bonding pad is electrically insulated from the second alignment pad, and wherein a lower surface of the first bonding pad is coplanar with a lower surface of the first alignment pad.
18. 18 . The semiconductor package of claim 17 , further comprising: a second semiconductor chip provided on an upper surface of the second alignment pad and an upper surface of the second bonding pad, the second semiconductor chip including a second wiring pattern, wherein the second wiring pattern is electrically connected to the second bonding pad, and the second wiring pattern is electrically insulated from the second alignment pad.
19. 19 . The semiconductor package of claim 17 , further comprising: a passivation layer which is provided on the upper surface of the first semiconductor chip and surrounds side faces of the first bonding pad and side faces of the first alignment pad.
20. 20 . The semiconductor package of claim 17 , wherein the lower surface of the first alignment pad is in contact with the upper surface of the first semiconductor chip.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation of U.S. patent application Ser. No. 17/199,703, filed on Mar. 12, 2021, which claims priority under 35 U.S.C. § 119 from Korean Patent Application No. 10-2020-0112307, filed on Sep. 3, 2020, in the Korean Intellectual Property Office, the entire contents of both of which are herein incorporated by reference. BACKGROUND 1. Technical Field Embodiments relates to a semiconductor package. 2. Description of the Related Art As the electronic industry becomes more highly developed, the demand for high integration of semiconductor elements increases. This causes various problems such as a decrease in process margin of an exposure process for defining fine patterns, and makes it more difficult to implement the semiconductor elements. Also, with the development of the electronic industry, the demand for high-speed of the semiconductor elements also increases. Various studies have been conducted to satisfy the demands for high integration and/or high speed of the semiconductor elements. SUMMARY Aspects of the present disclosure provide a semiconductor package having improved product reliability. Embodiments are directed to a semiconductor package including a first semiconductor chip including a first wiring structure, a first bonding pad and a first alignment key provided on the first wiring structure to be spaced apart from each other in a first direction, a second semiconductor chip including a second wiring structure which is spaced from the first semiconductor chip in a second direction different from the first direction and is opposite to the first wiring structure, a second bonding pad provided on the second wiring structure and electrically connected to the first bonding pad, and a second alignment key which is provided on the second wiring structure to be spaced apart from the second bonding pad in the first direction and does not overlap the first alignment key in the second direction, wherein the first wiring structure includes a first wiring pattern which is electrically connected to the first bonding pad and does not overlap the first alignment key and the second alignment key in the second direction, and the second wiring structure includes a second wiring pattern which is electrically connected to the second bonding pad and does not overlap the first alignment key and the second alignment key in the second direction. Embodiments are directed to a semiconductor package including a first semiconductor chip including a first wiring structure, a first passivation layer which includes a first alignment key and a first bonding pad provided on the first wiring structure to be spaced apart from each other in a first direction, a second passivation layer which is provided on the first passivation layer, and includes a second alignment key, and a second bonding pad directly joined to the first bonding pad, and a second semiconductor chip including a second wiring structure spaced apart from the first wiring structure in a second direction different from the first direction by the second passivation layer, wherein a surface on which the first alignment key and the first wiring structure are in contact forms a same plane as a surface on which the first bonding pad and the first wiring structure are in contact, a surface on which the second alignment key and the second wiring structure are in contact forms a same plane as a surface on which the second bonding pad and the second wiring structure are in contact, the first alignment key includes an alignment part, and an opening which penetrates the alignment part and exposes at least a part of the first wiring structure, and the second alignment key overlaps the opening in the second direction and does not overlap the alignment part in the second direction. Embodiments are directed to a semiconductor package including a substrate which includes a first face including a connection pad, and a second face opposite to the first face in a first direction, a first connection terminal electrically connected to the connection pad, on the first face of the substrate, a first semiconductor chip which includes a first wiring structure on the second face of the substrate, the first wiring structure including a first wiring region in which a first wiring pattern is provided and a first alignment region in which the first wiring pattern is not provided, and a first penetration electrode electrically connected to the first connection terminal and the first wiring pattern, a first passivation layer which includes a first bonding pad provided on the first wiring pattern of the first wiring structure and electrically connected to the first wiring pattern, and a first alignment key provided on the first alignment region of the first wiring structure, a second passivation layer which includes a second bonding pad directly joined to the first bonding pad, and a second alignment key which does not overlap the first al