US-12628660-B2 - Method for manufacturing electronic component device and electronic component device

US12628660B2US 12628660 B2US12628660 B2US 12628660B2US-12628660-B2

Abstract

A method for manufacturing an electronic component device including: preparing a wiring structure having a wiring portion including a metal wiring and an insulating layer and having two main surfaces opposite to each other, and a connection portion provided on one of the main surfaces of the wiring portion; fixing one or more conductor pins on the wiring substrate in a state in which the one or more conductor pins stand against the connection portion; mounting one or more electronic components on the wiring structure; and forming an encapsulation layer for encapsulating the electronic component and the conductor pin on the wiring structure.

Inventors

Tomoaki Shibata
Naoya Suzuki

Assignees

RESONAC CORPORATION

Dates

Publication Date: 20260512
Application Date: 20210831
Priority Date: 20200902

Claims (13)

1 . A method for manufacturing an electronic component device, comprising: preparing a wiring structure comprising a wiring portion comprising a metal wiring and an insulating layer, the wiring portion having two main surfaces opposite to each other, and a connection portion provided on a mounting surface selected from one of the two main surfaces of the wiring portion; fixing a plurality of conductor pins on the connection portion, wherein each of the plurality of conductor pins are formed as a metallic columnar-shaped body having a uniform width that is less than a length which extends perpendicular to the mounting surface of the wiring structure; mounting one or more electronic components on the wiring structure; and forming an encapsulation layer for encapsulating the one or more electronic components and the plurality of conductor pins on the wiring structure.
2 . The method according to claim 1 , wherein the one or more electronic components are arranged in a mounting region on the mounting surface of the wiring portion, some or all of the plurality of conductor pins are spaced apart from each other so as to form one row that surrounds the mounting region, and the encapsulation layer is filled between adjacent conductor pins in the one row.
3 . The method according to claim 2 , wherein the plurality of conductor pins additionally forms a second row that extends along an outer periphery of the mounting region and does not cross the one row.
4 . The method according to claim 3 , wherein conductor pins of the second row are offset from conductor pins of the one row that extend along the outer periphery of the mounting region, such that the plurality of conductor pins are arranged in a staggered arrangement.
5 . The method according to claim 2 , wherein a distance between the adjacent conductor pins in the one row is more than 50 μm and 250 μm or less.
6 . The method according to claim 1 , further comprising: forming a conductive shield film that covers the encapsulation layer and is connected to a distal end of each of the plurality of conductor pins.
7 . The method according to claim 1 , further comprising: exposing distal ends of the plurality of conductor pins by grinding the encapsulation layer from a surface opposite to the wiring structure.
8 . The method according to claim 1 , wherein the plurality of conductor pins are fixed on the wiring structure by: arranging a mask having openings on the mounting surface side of the wiring structure; and inserting the plurality of conductor pins through the openings in an upright position on the connection portion.
9 . The method according to claim 1 , wherein the plurality of conductor pins are fixed to the connection portion by melting a solder film covering an outer surface of the plurality of conductor pins along the length of the columnar-shaped body so that the solder film melts onto the connection portion, and electrically connects the plurality of conductor pins to the connection portion through the melted solder.
10 . The method according to claim 1 , wherein the columnar-shaped body of the plurality of conductor pins has a maximum width of 500 μm and a maximum length of 1000 μm.
11 . The method according to claim 1 , wherein the plurality of conductor pins are fixed on the wiring structure by: arranging a mask having openings on the mounting surface of the wiring portion; scattering the plurality of conductor pins on the mask; and vibrating the wiring structure and the mask, thereby inserting the plurality of conductor pins through the openings.
12 . A method for manufacturing an electronic component device, comprising: preparing a wiring structure including a wiring portion comprising a metal wiring and an insulating layer, the wiring portion having two main surfaces opposite to each other, and a connection portion provided on a mounting surface selected from one of the two main surfaces of the wiring portion; mounting one or more electronic components on the mounting surface of the wiring structure; fixing a plurality of conductor pins on the connection portion; and forming an encapsulation layer for encapsulating the one or more electronic components and the plurality of conductor pins on the wiring structure, wherein a first set of the plurality of conductor pins are spaced apart from each other so as to form a first row of pins that surrounds the one or more electronic components, a second set of the plurality of conductor pins are spaced apart from each other so as to form a second row of pins that surrounds the one or more electronic components without crossing the first row of pins, and the second set of pins are offset from the first set of pins such that the plurality of conductor pins are arranged in a staggered arrangement around the one or more electronic components.
13 . The method according to claim 12 , wherein each of the plurality of conductor pins are formed as a columnar-shaped body having a width that is less than half of a length which extends perpendicular to the mounting surface of the wiring structure.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a 35 U.S.C. § 371 national phase application of PCT/JP2021/031877, filed on Aug. 31, 2021, which claims priority to International Application No. PCT/JP2020/033259, filed on Sep. 2, 2020. TECHNICAL FIELD The present disclosure relates to a method for manufacturing an electronic component device and an electronic component device. BACKGROUND ART In various semiconductor packages, a conductive via penetrating through an encapsulation layer that encapsulates a semiconductor chip may be provided (for example, Patent Literature 1). A conventional method of forming a conductive via penetrating through the encapsulation layer includes an electroplating step. CITATION LIST Patent Literature Patent Literature 1: U.S. Patent Application Publication No. 2014/252646Patent Literature 2: International Publication WO 2017/057355Patent Literature 3: Japanese Patent No. 5494766Patent Literature 4: International Publication WO 2015/186744 SUMMARY OF INVENTION Technical Problem One aspect of the present disclosure makes it possible to manufacture an electronic component having a conductive via penetrating through an encapsulation layer that encapsulates the electronic component, with a simpler process. Solution to Problem According to an aspect of the present disclosure, there is provided a method for manufacturing an electronic component device including: preparing a wiring structure having a wiring portion including a metal wiring and an insulating layer and having two main surfaces opposite to each other, and a connection portion provided on one of the main surfaces of the wiring portion; fixing one or more conductor pins on the wiring structure in a state in which the one or more conductor pins stand against the connection portion; mounting one or more electronic components on the wiring structure; and forming an encapsulation layer for encapsulating the electronic component and the conductor pin on the wiring structure. According to another aspect of the present disclosure, there is provided an electronic component device including: a wiring structure having a wiring portion including a metal wiring and an insulating layer and having two main surfaces opposite to each other, and a connection portion provided on one of the main surfaces of the wiring portion; one or more electronic components mounted on the wiring structure; an encapsulation layer encapsulating the electronic component and being formed on the wiring structure; and one or more conductor pins penetrating through the encapsulation layer in a state in which the one or more conductor pins stand against the connection portion. Advantageous Effects of Invention According to an aspect of the present disclosure, an electronic component device having a conductive via penetrating through an encapsulation layer can be efficiently and easily manufactured with a small number of steps. The method according to an aspect of the present disclosure is also advantageous in that a conductive via having a narrow width and a predetermined height can be easily formed. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a process diagram showing an example of a method for manufacturing an electronic component device. FIG. 2 is a process diagram showing an example of a method for manufacturing an electronic component device. FIG. 3 is a process diagram showing an example of a method for manufacturing an electronic component device. FIG. 4 is a process diagram showing an example of a method for manufacturing an electronic component device. FIG. 5 is a process diagram showing an example of a method for fixing a conductor pin onto a wiring structure. FIG. 6 is a process diagram showing an example of a method for fixing a conductor pin onto a wiring structure. FIG. 7 is a plan view showing an example of an electronic component device. FIG. 8 is a plan view showing an example of an electronic component device. FIG. 9 is a micrograph of a wiring structure and conductor pins fixed on the wiring structure. DESCRIPTION OF EMBODIMENTS The present invention is not limited to the following examples. FIGS. 1, 2, 3, and 4 are process diagrams showing an example of a method for manufacturing an electronic component device. The method shown in FIGS. 1 to 4 includes: preparing a wiring structure 60 having a wiring portion 6 that includes a metal wiring 61 and an insulating layer 62 and has two main surfaces 6S1 and 6S2 opposite to each other, and a plurality of connection portions 65, 66, and 67 provided on one main surface 6S1 of the wiring portion 6; fixing two or more conductor pins 5 on the wiring structure 60 in a state in which the two or more conductor pins 5 stand against the connection portion 67; mounting a chip component 2 and a chip-type passive component 3 as electronic components on the wiring structure 60; and forming an encapsulation layer 7 that encapsulates the electronic components (the chip component 2 and the passive component 3)