US-12628661-B2 - Chip package having die pad with protective layer

US12628661B2US 12628661 B2US12628661 B2US 12628661B2US-12628661-B2

Abstract

A chip package having die pads with protective layers is provided. At least one protective layer is covering and arranged at a peripheral zone of at least one die pad for minimizing area of the die pad exposed outside as well as shielding and protecting the peripheral zone of the die pad. A weld zone of the die pad is not covered by the protective layer so that the weld zone of the die pad is exposed. In a crossed-over state, one of bonding wires crossing one of the die pads with a corresponding connection pad of a carrier plate will not get across a second upper space defined by the weld zone of the rest of the die pads. Thereby the one of the bonding wires can be more isolated by the protective layers on the peripheral zones of the rest of the die pads.

Inventors

Hong-Chi Yu
Chun-Jung Lin
Ruei-Ting Gu

Assignees

WALTON ADVANCED ENGINEERING, INC.

Dates

Publication Date: 20260512
Application Date: 20230905
Priority Date: 20220919

Claims (2)

1 . A chip package having die pads with protective layers comprising: a chip unit provided with a surface; a plurality of the die pads disposed on the surface of the chip unit while a weld zone and a peripheral zone surrounding the weld zone are defined on each of the die pads; wherein the weld zone of the die pad is for allowing welding of one end of at least one bonding wire generated during wire bonding of the chip package; wherein a space located over the die pad is defined as a first upper space while a space located over the weld zone of the die pad is defined as a second upper space which is smaller than the first upper space; and the at least one protective layer which is covering and arranged at the peripheral zone of at least one of the die pads for minimizing area of the die pad exposed outside as well as shielding and protecting the peripheral zone of the die pad; wherein the weld zone of the die pad is not covered by the protective layer so that the weld zone of the die pad is exposed; wherein the protective layer on the chip package is further covering the peripheral zone of a part of the die pads of the chip package; wherein the chip package is located at a carrier plate which is provided with a plurality of connection pads for allowing welding of one end of the bonding wire generated during wire bonding of the carrier plate; the connection pad and the corresponding die pad of the chip package are in a one-to-one corresponding relationship; wherein while performing wire bonding on the chip package and the carrier plate, the weld zone of the die pad on the chip package and the corresponding connection pad on the carrier plate are electrically connected by the bonding wire generated during the wire bonding; thereby the bonding wire goes across from the weld zone of the die pad to the corresponding connection pad to be in a crossed-over state while the chip package and the carrier plate are electrically connected; wherein under the crossed-over state, one of the bonding wires connecting one of the die pads with the corresponding connection pad will not cross the second upper space defined by the weld zone of the rest of the die pads; thereby the one of the bonding wires is more isolated by the protective layer on the peripheral zone of the rest of the die pads.
2 . The chip package as claimed in claim 1 , wherein the die pad is made of aluminum materials.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This non-provisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No(s). 111135356 filed in Taiwan, R.O.C. on Sep. 19, 2022, the entire contents of which are hereby incorporated by reference. BACKGROUND OF THE INVENTION This is chip package, especially to a chip package having die pads with protective layers. In the semiconductor field, a conventional chip package is electrically connected with a carrier plate by a bonding wire generated during wire bonding. Refer to FIG. 11 and FIG. 12, during wire bonding between a chip package 4 and a carrier plate 2, a plurality of die pads 4a on the chip package 4 are electrically connected with a plurality of corresponding connection pads 2a on the carrier plate 2 by a plurality of bonding wires 3 generated during wire bonding. The respective bonding wires 3 go across from the die pads 4a to the corresponding connection pads 2a to be in a crossed-over state. However, while in the crossed-over state, the bonding wire 3 may cross over a space on top of the other die pads 4a so that signals travelling through the bonding wire 3 and the die pads 4a interfere with each other. The operation of an electronic system may be disturbed and even ruined. Moreover, in order to avoid signal interference between the bonding wire 3 and the respective die pads 4a, manufacturers need to re-arrange positions of the connection pads 2a on the carrier plate 2 or related circuit. Thereby manufacturing cost is increased. SUMMARY OF THE INVENTION Therefore, it is a primary object of the present invention to provide a chip package having die pads with protective layers in which at least one protective layer is covering a peripheral zone of at least one die pad for minimizing area of the respective die pads exposed outside as well as shielding and protecting the peripheral zone of the respective die pads. A weld zone of the respective die pads is not covered by the protective layer so that the weld zone of the respective die pads is exposed. In a crossed-over state, one of bonding wires connecting one of the die pads with a corresponding connection pad of a carrier plate will not get across a second upper space defined by the weld zone of the rest of the die pads. Thereby the bonding wire can be more isolated by the respective protective layers on the peripheral zones of other die pads than ever. The problem of signals through the die pad and the bonding wire interfering with each other can be solved. In order to achieve the above object, a chip package having die pads with protective layers according to the present invention includes a chip unit, a plurality of die pads, and at least one protective layer. The chip unit has one surface on which the respective die pads are disposed. A weld zone and a peripheral zone surrounding the weld zone are defined on each of the die pads. The weld zone of the die pad is for allowing welding of one end of at least one bonding wire generated during wire bonding. A space located over the die pad is defined as a first upper space while a space located over the weld zone of the die pad is defined as a second upper space which is smaller than the first upper space. The protective layer is covering and arranged at the peripheral zone of the die pad for minimizing area of the respective die pads exposed outside as well as shielding and protecting the peripheral zone of the respective die pads. The weld zone of the respective die pads is not covered by the protective layer so that the weld zone of the respective die pads is exposed. The chip package is located at a carrier plate which is provided with a plurality of connection pads for allowing welding of one end of the bonding wire generated during wire bonding of the carrier plate. The connection pads and the corresponding die pads of the chip package are in a one-to-one corresponding relationship. The weld zone of the respective die pads on the chip package and the corresponding connection pads on the carrier plate are electrically connected by the respective bonding wires generated during the wire bonding. The bonding wire goes across from the weld zone of the respective die pads to the corresponding connection pad to be in a crossed-over state. Thereby the chip package and the carrier plate are electrically connected. Under the crossed-over state, one of the bonding wires connecting one of the die pads with the corresponding connection pad will not cross the second upper space defined by the weld zone of the rest of the die pads. Thereby the bonding wire can be more isolated by the protective layer on the peripheral zone of other die pads than ever. Preferably, the protective layers on the chip package are further covering the peripheral zones of a part of the die pads of the chip package. Preferably, the respective protective layers on the chip package are further covering the peripheral zones of all of the die pads of the chip package, and