US-12628662-B2 - Semiconductor chip, chip system, method of forming a semiconductor chip, and method of forming a chip system

US12628662B2US 12628662 B2US12628662 B2US 12628662B2US-12628662-B2

Abstract

A semiconductor chip is provided. The semiconductor chip may include a front side including a control chip contact and a first controlled chip contact, a back side including a second controlled chip contact, a backside metallization formed over the back side in contact with the second controlled chip contact, and a stop region extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side. The contact portion is configured to be attached to an electrically conductive structure by a die attach material, a surface of the stop region is recessed with respect to a surface of the contact portion, and/or the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion.

Inventors

Hooi Boon Teoh
Ralf Otremba
Martin Pölzl
Ying Pok Sam
Xaver Schlögel
Chee Voon Tan
Hao Zhuang
Oliver Blank
Paul Armand Calo
Markus Dinkel
Josef Höglauer
Daniel Hólzl
Wee Aun JASON LIM
Gerhard Thomas Nöbauer

Assignees

INFINEON TECHNOLOGIES AG

Dates

Publication Date: 20260512
Application Date: 20221221
Priority Date: 20220117

Claims (16)

1 . A semiconductor chip, comprising: a front side; a back side comprising a second controlled chip contact; a backside metallization formed over the back side in contact with the second controlled chip contact; and a stop region on the back side extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side, wherein the contact portion is configured to be attached to an electrically conductive structure by a die attach material; wherein at least a portion of a surface of the stop region is recessed with respect to a surface of the contact portion and the surface of the stop region has a lower wettability with respect to the die attach material than an entirety of the contact portion.
2 . The semiconductor chip of claim 1 , wherein the backside metallization is a structured metallization.
3 . The semiconductor chip of claim 1 , wherein the backside metallization is at least partially removed in the stop region.
4 . The semiconductor chip of claim 1 , wherein the stop region comprises the recessed surface, which is recessed with respect to the surface of the contact portion by between 1 and 30 μm.
5 . The semiconductor chip of claim 1 , wherein the stop region comprises at its surface at least one of a group of low-wettability-materials, the group comprising: bare silicon; an oxide; and a polymer.
6 . The semiconductor chip of claim 1 , wherein the stop region comprises at its surface at least one of a group of oxides, the group comprising: silicon oxide; titanium oxide; and nickel oxide.
7 . The semiconductor chip of claim 1 , wherein the stop region is formed circumferentially around the contact portion.
8 . A chip system, comprising: the semiconductor chip of claim 1 ; and the electrically conductive structure, wherein the semiconductor chip is attached to the electrically conductive structure by the die attach material.
9 . The chip system of claim 8 , wherein the semiconductor chip at least partially extends horizontally to or beyond an outer edge of the electrically conductive structure.
10 . A method of forming a chip system, the method comprising: attaching a semiconductor chip of claim 1 to an electrically conductive structure by a die attach material.
11 . The semiconductor chip of claim 1 , wherein the front side includes a control chip contact and a first controlled chip contact.
12 . A method of forming a semiconductor chip, the method comprising: forming a backside metallization over a back side of a semiconductor chip, wherein the semiconductor chip comprises a front side and the back side comprising a second controlled chip contact, and the backside metallization is formed in contact with the second controlled chip contact; and forming a stop region on the back side extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side, wherein the contact portion is configured to be attached to an electrically conductive structure by a die attach material; wherein at least a portion of a surface of the stop region is recessed with respect to a surface of the contact portion and the surface of the stop region has a lower wettability with respect to the die attach material than an entirety of the contact portion.
13 . The method of claim 12 , wherein the forming the backside metallization comprises forming a structured backside metallization.
14 . The method of claim 12 , further comprising: at least partially removing the backside metallization in the stop region.
15 . The method of claim 12 , further comprising: forming a low-wettability-material at a surface of the stop region by at least one of a group of processes, the group comprising: etching and/or laser processing the backside metallization for exposing bulk semiconductor material of the chip and/or a seed layer of the backside metallization; depositing a layer of the low wettability material; plasma processing of the bulk semiconductor material of the chip or of a deposited layer; and printing or spraying of the low wettability material.
16 . A semiconductor chip, comprising: a front side; a back side comprising a second controlled chip contact; a backside metallization formed over the back side in contact with the second controlled chip contact; and a stop region on the back side extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side, wherein the contact portion is configured to be attached to an electrically conductive structure by a die attach material; wherein at least a portion of a surface of the stop region is recessed with respect to a surface of the contact portion and the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion; and wherein the stop region comprises at its surface at least one of a group of low-wettability-materials, the group comprising: a polymer; and an oxide comprising at least one of a group of oxides comprising: silicon oxide; titanium oxide; and nickel oxide.

Description

CROSS-REFERENCE TO RELATED APPLICATION This Utility Patent Application claims priority to German Patent Application No. 10 2022 100 969.6, filed Jan. 17, 2022, which is incorporated herein by reference. TECHNICAL FIELD Various embodiments relate generally to a semiconductor chip, chip system, method of forming a semiconductor chip, and method of forming a chip system. BACKGROUND FIG. 1 illustrates how a chip package 100 including a chip 102 (also referred to as die) is formed according to a prior art. The processes include, from top left to bottom right of the panels illustrating the process, a depositing of a soft solder 106, a die 102 attach, another solder 110 depositing process on the chip 102 top, a clip 112 attach process, and a molding process with a mold material 114. Here, the chip size may be limited by the die pad (also referred to as die paddle) size (in other words, the pad to which the chip 102 is attached using the solder 106): a maximum chip size may be defined and limited (in X and Y direction) by a clearance between the die pad edge and chip edge. The clearance of chip to die pad may be critical to ensure sufficient space for solder 106 bleedout, A2 dendrite growth and to minimize delamination after stress. If a larger-than-standard chip 102 is to be used, the prior art typically employs one of two techniques to make this possible: Either to use a larger dedicated etched leadframe 104 (that provides the die pad), which incurs higher costs, or to use a source-down configuration, wherein a chip front side is attached to the die pad of the leadframe 104, which means that the structurization of the source pad confines the solder 106 under the chip 102, but increases a risk of gate solder voids, causes a source active area reduction due to flip chip design rules, and increases the cost because the source down technology regularly incurs higher costs than standard die bond technology. SUMMARY A semiconductor chip is provided. The semiconductor chip may include a front side including a control chip contact and a first controlled chip contact, a back side including a second controlled chip contact, a backside metallization formed over the back side in contact with the second controlled chip contact, and a stop region extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side, wherein the contact portion is configured to be attached to an electrically conductive structure by a die attach material, wherein a surface of the stop region is recessed with respect to a surface of the contact portion, and/or the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which: FIG. 1 illustrates a method of forming a chip package according to a prior art and chip size constraints relevant for the chip package of the prior art; FIG. 2 shows a schematic cross-sectional view of a semiconductor chip in accordance with various embodiments; FIG. 3 illustrates a method of forming a chip system in accordance with various embodiments; FIG. 4 shows partial schematic cross-sectional views of four chip systems in accordance with various embodiments; FIG. 5 shows two partial cross-sectional images of a chip system in accordance with various embodiments; each of FIGS. 6, 7 and 8 illustrates a method of forming a semiconductor chip in accordance with various embodiments as a sequence of schematic process images; FIG. 9A illustrates, as a partial schematic cross-sectional view, a chip system with a chip in a source-down configuration in accordance with various embodiments; FIG. 9B illustrates, as a partial schematic cross-sectional view, a chip system with a chip in a source-up configuration in accordance with various embodiments; each of FIG. 10A and FIG. 10B illustrates, as schematic cross-sectional views, a chip system in accordance with various embodiments; FIG. 11 shows a process flow of a method of forming a semiconductor chip in accordance with various embodiments; and FIG. 12 shows a process flow of a method of forming a chip system in accordance with various embodiments. DESCRIPTION The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration”. Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or adv