US-12628667-B2 - Semiconductor package substrate having front and back side resin-filled trenches and method of manufacturing the same

US12628667B2US 12628667 B2US12628667 B2US 12628667B2US-12628667-B2

Abstract

Provided are a semiconductor package substrate, a method of manufacturing the semiconductor package substrate, and a semiconductor package. According to one embodiment of the present disclosure, a semiconductor package substrate includes a base substrate having a lower surface in which a first trench is provided and an upper surface in which a second trench and a third trench are provided, including a circuit pattern and a conductive material; a first resin arranged in the first trench; and a second resin arranged in the second trench and the third trench, wherein the second trench exposes at least a part of the first resin.

Inventors

Dong Jin Yoon
Sung Il Kang
In Seob BAE
Seok Kyu SEO
Dong Young PYEON

Assignees

HAESUNG DS CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20220907
Priority Date: 20210915

Claims (15)

1 . A semiconductor package substrate comprising: a base substrate having a lower surface in which a first trench is provided and an upper surface in which a second trench and a third trench are provided, including a circuit pattern and a conductive material, wherein the third trench is separate and distinct from the second trench; a first resin arranged in the first trench; and a second resin arranged in the second trench and the third trench, wherein the second trench exposes at least a part of the first resin, and wherein an upper surface of the second resin is level with the upper surface of the base substrate, a lower surface of the first resin is level with the lower surface of the base substrate, and the third trench is offset from the first trench so as to be separate from each part of the first trench.
2 . The semiconductor package substrate of claim 1 , further comprising a mounting portion which is arranged on the upper surface of the base substrate and on which a semiconductor chip is mounted, wherein the third trench is arranged to be farther from the mounting portion than the second trench, and a width of the third trench is greater than a width of the second trench.
3 . The semiconductor package substrate of claim 1 , wherein the first resin and the second resin are provided as a same type of resin.
4 . The semiconductor package substrate of claim 1 , further comprising a fourth trench arranged in the upper surface of the base substrate, wherein the fourth trench is arranged along a cutting line.
5 . The semiconductor package substrate of claim 4 , wherein the second resin is arranged in the fourth trench.
6 . A method of manufacturing a semiconductor package substrate, the method comprising: forming a first trench in a lower surface of a base substrate formed of a conductive material; filling the first trench with a first resin, wherein a lower surface of the first resin is level with the lower surface of the base substrate; forming a second trench and a third trench in an upper surface of the base substrate, wherein the third trench is separate and distinct from the second trench; and filling the second trench and the third trench with a second resin, wherein an upper surface of the second resin is level with the upper surface of the base substrate, wherein the second trench is formed to expose at least a part of the first resin while the third trench is offset from the first trench so as to be separate from each part of the first trench.
7 . The method of claim 6 , wherein the upper surface of the base substrate includes a mounting portion on which a semiconductor chip is mounted, the third trench is arranged to be farther from the mounting portion than the second trench, and a width of the third trench is greater than a width of the second trench.
8 . The method of claim 6 , wherein the first resin and the second resin are formed of a same type of resin.
9 . The method of claim 6 , wherein a fourth trench is arranged in the upper surface of the base substrate, and the fourth trench is arranged along a cutting line.
10 . The method of claim 9 , wherein a fifth trench is arranged in the lower surface of the base substrate, and the fifth trench overlaps the fourth trench.
11 . A semiconductor package comprising: a base substrate having a lower surface in which a first trench is provided and an upper surface in which a second trench and a third trench are provided, having a circuit pattern formed in the base substrate, and formed of a conductive material, wherein the third trench is separate and distinct from the second trench; a first resin arranged in the first trench; a second resin arranged in the second trench and the third trench; a semiconductor chip arranged on the upper surface of the base substrate; and a cover configured to cover the semiconductor chip and including a bonding portion bonded to the base substrate, wherein the bonding portion is bonded to the second resin arranged in the third trench, and wherein an upper surface of the second resin is level with the upper surface of the base substrate, a lower surface of the first resin is level with the lower surface of the base substrate, and the third trench is offset from the first trench so as to be separate from each part of the first trench.
12 . The semiconductor package of claim 11 , further comprising an adhesive member arranged between the bonding portion and the second resin.
13 . The semiconductor package of claim 11 , wherein a width of the third trench is greater than a width of the second trench.
14 . The semiconductor package of claim 11 , wherein the first resin and the second resin are formed of a same type of resin.
15 . The semiconductor package of claim 11 , further comprising a fourth trench provided in an edge of the base substrate, wherein the second resin is arranged in the fourth trench.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0123112, filed on Sep. 15, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND 1. Field Embodiments of the present disclosure relate to a semiconductor package substrate, a method of manufacturing the semiconductor package substrate, and a semiconductor package. 2. Description of the Related Art A semiconductor device is packaged on a semiconductor package substrate to be used, and the semiconductor package substrate used for packaging includes a micro circuit pattern and/or input/output (I/O) terminals. As high performance and/or high integration of semiconductor devices and miniaturization and/or high performance of electronic devices using the semiconductor devices are realized, a line width and complexity of a micro circuit pattern of a semiconductor package substrate narrows and increases. In recent years, a method of manufacturing a semiconductor package substrate by filling a conductive base substrate with an insulating material has been introduced to simplify a manufacturing process of the semiconductor package substrate. SUMMARY Embodiments of the present disclosure provide a semiconductor package substrate and a semiconductor package with excellent reliability, which are manufactured by a simple process, and a method of manufacturing the semiconductor package substrate. The objects to be achieved by the present disclosure are not limited to the objects described above, and other objects not described will be clearly understood by those skilled in the art from descriptions of the present disclosure. Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure. According to one aspect of the present disclosure, a semiconductor package substrate includes a base substrate having a lower surface in which a first trench is provided and an upper surface in which a second trench and a third trench are provided, including a circuit pattern and a conductive material; a first resin arranged in the first trench; and a second resin arranged in the second trench and the third trench, wherein the second trench exposes at least a part of the first resin. In one embodiment, the semiconductor package substrate may further include a mounting portion which is arranged on the upper surface of the base substrate and on which a semiconductor chip is mounted, wherein the third trench may be arranged to be farther from the mounting portion than the second trench, and a width of the third trench may be greater than a width of the second trench. In one embodiment, the first resin and the second resin may be provided as a same type of resin. In one embodiment, the semiconductor package substrate may further include a fourth trench arranged in the upper surface of the base substrate, wherein the fourth trench may be arranged along a cutting line. In one embodiment, the second resin may be arranged in the fourth trench. According to another aspect of the present disclosure, a method of manufacturing a semiconductor package substrate includes forming a first trench in a lower surface of a base substrate formed of a conductive material, filling the first trench with a first resin, forming a second trench and a third trench in an upper surface of the base substrate, and filling the second trench and the third trench with a second resin, wherein the second trench is formed to expose at least a part of the first resin. In one embodiment, the upper surface of the base substrate may include a mounting portion on which a semiconductor chip is mounted, the third trench may be arranged to be farther from the mounting portion than the second trench, and a width of the third trench may be greater than a width of the second trench. In one embodiment, the first resin and the second resin may be formed of a same type of resin. In one embodiment, a fourth trench may be arranged in the upper surface of the base substrate further, and the fourth trench may be arranged along a cutting line. In one embodiment, a fifth trench may be arranged in the lower surface of the base substrate, and the fifth trench may overlap the fourth trench. According to another aspect of the present disclosure, a semiconductor package includes a base substrate having a lower surface in which a first trench is provided and an upper surface in which a second trench and a third trench are provided, having a circuit pattern formed in the base substrate, and formed of a conductive material; a first resin arranged in the first trench; a second resin arranged in the second trench and the third trench; a semiconductor chip arranged on the upper surface of the base substrate; and a cover configured to