US-12628668-B2 - Semiconductor package

US12628668B2US 12628668 B2US12628668 B2US 12628668B2US-12628668-B2

Abstract

A semiconductor package includes a connection substrate with a cavity, a first semiconductor chip and a second semiconductor chip on the connection substrate, a third semiconductor chip in the cavity of the connection substrate, the first semiconductor chip and the second semiconductor chip being on the third semiconductor chip and being connected to each other through the third semiconductor chip, and a molding layer that covers the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip, wherein the third semiconductor chip includes first bumps that are exposed through the molding layer and are connected to the first semiconductor chip and the second semiconductor chip.

Inventors

Myungsam Kang

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20230214
Priority Date: 20220720

Claims (20)

1 . A semiconductor package, comprising: a connection substrate with a cavity; a first semiconductor chip and a second semiconductor chip each mounted on the connection substrate; a third semiconductor chip in the cavity of the connection substrate, the first semiconductor chip and the second semiconductor chip each having a portion vertically overlapping the third semiconductor chip and being connected to each other through the third semiconductor chip; and a molding layer that covers an upper surface of the third semiconductor chip and an upper surface of the connection substrate, the molding layer being disposed below the first semiconductor chip and the second semiconductor chip, wherein the third semiconductor chip includes first bumps that penetrate through and protrude from the molding layer, a first set of the first bumps being connected to the first semiconductor chip and a second set of the first bumps being connected to the second semiconductor chip.
2 . The semiconductor package as claimed in claim 1 , wherein the third semiconductor chip has a first thickness, the connection substrate has a second thickness, and the first thickness is equal to the second thickness.
3 . The semiconductor package as claimed in claim 2 , wherein the first thickness of the third semiconductor chip is in a range of about 100 μm to about 300 μm.
4 . The semiconductor package as claimed in claim 1 , wherein each of the first bumps has a pillar shape and a diameter of each of the first bumps is in a range of about 10 μm to about 40 μm.
5 . The semiconductor package as claimed in claim 4 , further comprising an oxidation barrier layer that covers a surface of each of the first bumps.
6 . The semiconductor package as claimed in claim 1 , wherein the third semiconductor chip includes a wiring layer connected to the first bumps, the wiring layer connecting the first semiconductor chip to the second semiconductor chip, and the wiring layer including a plurality of wiring lines.
7 . The semiconductor package as claimed in claim 6 , wherein the third semiconductor chip further includes a plurality of through vias below the wiring layer and connected to the wiring layer, one of the plurality of through vias is configured to transmit a first signal to the first semiconductor chip, and another of the plurality of through vias is configured to transmit a second signal to the second semiconductor chip.
8 . The semiconductor package as claimed in claim 7 , further comprising: a redistribution substrate below the connection substrate and the third semiconductor chip, the redistribution substrate being connected to the plurality of through vias; a solder resist layer that covers a bottom surface of the redistribution substrate and exposes a portion of the bottom surface of the redistribution substrate; and a plurality of external connection terminals on the bottom surface of the redistribution substrate, each of the plurality of external connection terminals being located at a respective location of the bottom surface exposed by the solder resist layer.
9 . The semiconductor package as claimed in claim 1 , wherein: a first portion of the connection substrate is connected to the first semiconductor chip, a second portion of the connection substrate is connected to the second semiconductor chip, and the connection substrate includes: a conductive pillar that penetrates through the connection substrate, and a second bump on a top surface of the conductive pillar, the second bump being penetrating through and extending from the molding layer, and the second bump being connected to one of the first semiconductor chip and the second semiconductor chip.
10 . The semiconductor package as claimed in claim 9 , wherein the first bumps and the second bump each have the same vertical length.
11 . The semiconductor package as claimed in claim 10 , wherein the vertical length of the first bumps and the second bump is in a range of about 10 μm to about 20 μm.
12 . The semiconductor package as claimed in claim 9 , wherein the second bump has a pillar shape and a diameter of the second bump is in a range of 50 μm to 100 μm.
13 . The semiconductor package as claimed in claim 9 , further comprising an oxidation barrier layer that covers a surface of the second bump.
14 . A semiconductor package, comprising: a connection substrate with a cavity; a first semiconductor chip and a second semiconductor chip mounted on the connection substrate; a third semiconductor chip in the cavity of the connection substrate, the first semiconductor chip and the second semiconductor chip each having a chip portion vertically overlapping the third semiconductor chip and being connected to each other through the third semiconductor chip; and a molding layer that covers an upper surface of the third semiconductor chip and an upper surface of the connection substrate, the molding layer being disposed below the first semiconductor chip and the second semiconductor chip, wherein the third semiconductor chip includes first bumps that penetrate through and protrude from the molding layer, a first set of the first bumps being connected to the first semiconductor chip and a second set of the first bumps being connected to the second semiconductor chip, and wherein the connection substrate includes second bumps that penetrate through and protrude from the molding layer, a first set of the second bumps being connected to the first semiconductor chip and a second set of the second bumps being connected to the second semiconductor chip.
15 . The semiconductor package as claimed in claim 14 , wherein: the third semiconductor chip and the connection substrate each have the same thickness, and the first bumps and the second bumps each have the same vertical length.
16 . The semiconductor package as claimed in claim 15 , wherein: the thickness of the third semiconductor chip and the connection substrate is in a range of about 100 μm to about 300 μm, and the vertical length of the first bumps and the second bumps is in a range of about 10 μm to about 20 μm.
17 . The semiconductor package as claimed in claim 14 , wherein each of the first bumps and each of the second bumps has a pillar shape, a diameter of each of the first bumps being in a range of about 10 μm to about 40 μm, and a diameter of each of the second bumps being in a range of about 50 μm to about 100 μm.
18 . The semiconductor package as claimed in claim 14 , further comprising an oxidation barrier layer that covers a surface of each of the first bumps and each of the second bumps.
19 . The semiconductor package as claimed in claim 14 , further comprising a redistribution substrate below the third semiconductor chip, the third semiconductor chip further including: a wiring layer in the third semiconductor chip, the wiring layer being connected to the first bumps and connecting the first semiconductor chip and the second semiconductor chip to each other; and a through via in the third semiconductor chip below the wiring layer, the through via connecting the wiring layer and the redistribution substrate to each other.
20 . A semiconductor package, comprising: a connection substrate with a cavity; a first semiconductor chip and a second semiconductor chip on the connection substrate and having a portion vertically overlapping the cavity; a third semiconductor chip in the cavity of the connection substrate; and a molding layer between the third semiconductor chip and the connection substrate, the molding layer surrounding the third semiconductor chip and a top surface of the connection substrate, wherein the first semiconductor chip is mounted on the molding layer and is adjacent to a first side of the connection substrate, the first semiconductor chip being connected to the connection substrate and the third semiconductor chip, wherein the second semiconductor chip is mounted on the molding layer and is adjacent to a second side of the connection substrate, the second semiconductor chip being connected to the connection substrate and the third semiconductor chip, wherein the third semiconductor chip includes: first bumps protruding from a top surface of the third semiconductor chip to penetrate through and extend from the molding layer, a first set of the first bumps connected to a bottom surface of the first semiconductor chip and a second set of the first bumps connected to a bottom surface of the second semiconductor chip, and a first oxidation barrier layer that covers a surface of each of the first bumps, wherein the connection substrate includes: second bumps protruding from the top surface of the connection substrate to penetrate through and extend from the molding layer, a first set of the second bumps connected to the bottom surface of the first semiconductor chip and a second set of the second bumps connected to the bottom surface of the second semiconductor chip, and a second oxidation barrier layer that covers a surface of each of the second bumps, wherein the third semiconductor chip has the same thickness as the thickness of the connection substrate, wherein each of the first bumps and each of the second bumps has the same vertical length, wherein a diameter of each of the first bumps is in a range of about 10 μm to about 40 μm, and wherein a diameter of each of the second bumps is in a range of about 50 μm to about 100 μm.

Description

CROSS-REFERENCE TO RELATED APPLICATION This U.S. nonprovisional application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2022-0089282, filed on Jul. 20, 2022, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety. BACKGROUND 1. Field The present disclosure relates to a semiconductor package. 2. Description of the Related Art A semiconductor package may be provided to implement an integrated circuit chip to qualify for use in electronic products. Typically, in the semiconductor package, a semiconductor chip is mounted on a printed circuit board (PCB) and bonding wires or bumps are used to electrically connect the semiconductor chip to the PCB. With the recent development of electronic industry, the semiconductor package is variously developed to have a compact size, small weight, and/or low manufacturing cost. In addition, semiconductor packages may be implemented as high-capacity mass storage devices. SUMMARY According to some embodiments, a semiconductor package may include a connection substrate that has a cavity in the connection substrate; a third semiconductor chip in the connection substrate; a first semiconductor chip and a second semiconductor chip that are on the third semiconductor chip and are connected to each other through the third semiconductor chip; and a molding layer that covers the first, second, and third semiconductor chips. The third semiconductor chip may include a plurality of first bumps that are exposed from the molding layer and are connected to the first and second semiconductor chips. According to some embodiments, a semiconductor package may include a connection substrate that has a cavity in the connection substrate; a third semiconductor chip in the cavity; a first semiconductor chip and a second semiconductor chip that are on the third semiconductor chip and are connected to each other through the third semiconductor chip; and a molding layer that covers the first, second, and third semiconductor chips. The third semiconductor chip may include a plurality of first bumps exposed from the molding layer and connected to the first and second semiconductor chips. The connection substrate may include a plurality of second bumps exposed from the molding layer and connected to the first and second semiconductor chips. According to some embodiments, a semiconductor package may include a connection substrate that has a cavity in the connection substrate; a third semiconductor chip in the cavity; a molding layer between the third semiconductor chip and the connection substrate, the molding layer surrounding the third semiconductor chip and a top surface of the connection substrate; a first semiconductor chip on the molding layer and adjacent to one side of the connection substrate, the first semiconductor chip being connected to the connection substrate and the third semiconductor chip; and a second semiconductor chip on the molding layer and adjacent to another side of the connection substrate, the second semiconductor chip being connected to the connection substrate and the third semiconductor chip. The third semiconductor chip may include a plurality of first bumps that protrude from a top surface of the third semiconductor chip and are connected to bottom surfaces of the first and second semiconductor chips; and a first oxidation barrier layer that covers a surface of the first bump. The connection substrate may include a plurality of second bumps that protrude from the top surface of the connection substrate and are connected to the bottom surface of one of the first and second semiconductor chips; and a second oxidation barrier layer that covers a surface of the second bump. The third semiconductor chip may have a thickness the same as a thickness of the connection substrate. The first bump and the second bump may have the same vertical length. A diameter of the first bump may be in a range of about 10 μm to about 40 μm. A diameter of the second bump may be in a range of about 50 μm to about 100 μm. BRIEF DESCRIPTION OF THE DRAWINGS Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which: FIG. 1 illustrates a plan view of a semiconductor package according to some embodiments. FIG. 2 illustrates a cross-sectional view along line I-I′ of FIG. 1. FIGS. 3 to 11 illustrate cross-sectional views of stages in a method of fabricating a semiconductor package according to some embodiments. DETAILED DESCRIPTION FIG. 1 illustrates a plan view showing a semiconductor package according to some embodiments. FIG. 2 illustrates a cross-sectional view taken along line I-I′ of FIG. 1, showing a semiconductor package according to some embodiments. Referring to FIGS. 1 and 2, a semiconductor package 1 may include a connection substrate 100, a first semiconductor chip CH1, a second semiconductor chip CH2, a thir