US-12628670-B2 - Radio frequency (RF) interconnect configuration for substrate and surface mount device

US12628670B2US 12628670 B2US12628670 B2US 12628670B2US-12628670-B2

Abstract

Aspects of the subject disclosure may include, for example, system, comprising a substrate having an interconnect in or on a surface of the substrate, a riser disposed over the surface, the riser being configured with one or more through riser vias for coupling to the interconnect, a device positioned over the surface, the device having one or more conductive contacts residing in a plane of the device, and one or more wire bonds coupling the one or more through riser vias with the one or more conductive contacts thereby enabling connectivity of the interconnect to be raised toward or to the plane of the device such that at least one of the one or more wire bonds has a limited physical length. Other embodiments are disclosed.

Inventors

Michael Vitic
Maxime Jacques
Raphaël BEAUPRÉ-LAFLAMME

Assignees

CIENA CORPORATION

Dates

Publication Date: 20260512
Application Date: 20230303

Claims (20)

1 . A system, comprising: a substrate having an interconnect in or on a surface of the substrate; a riser disposed over the surface and partially over the interconnect, the riser being configured with one or more through riser vias for coupling to the interconnect, the riser having first and second ends, wherein the interconnect extends beyond the first end of the riser for coupling with one or more components; a device positioned over the surface and adjacent to the second end of the riser, the device having one or more conductive contacts residing in a plane of the device; and one or more wire bonds coupling the one or more through riser vias with the one or more conductive contacts thereby enabling connectivity of the interconnect to be raised toward or to the plane of the device such that at least one of the one or more wire bonds has a length that is less than a threshold length.
2 . The system of claim 1 , wherein the one or more components include one of a driver, a digital signal processor or an application specific integrated circuit, and wherein the riser is composed of one of: silicon such that the one or more through riser vias comprise through silicon vias (TSVs); glass such that the one or more through riser vias comprise through glass vias (TGVs); ceramic such that the one or more through riser vias comprise through ceramic vias; thin-film aluminum nitride (AlN) such that the one or more through riser vias comprise through AlN vias; thin-film aluminum oxide (Al2O3) such that the one or more through riser vias comprise through Al2O3 vias; or an active material or device such that the one or more through riser vias comprise vias through that active material or device.
3 . The system of claim 1 , wherein the device comprises a surface mount electrical-to-optical (E-O) or optical-to-electrical (O-E) transmitter or receiver, a thin-film lithium niobate (TFLN) modulator, an amplifier or an active circuit, a sensor, or a combination thereof, and wherein the substrate comprises an organic substrate or a printed circuit board (PCB).
4 . The system of claim 1 , wherein the interconnect comprises a radio frequency (RF) interconnect, and wherein the one or more through riser vias are composed of one or more conductive materials.
5 . The system of claim 1 , wherein the riser includes a redistribution layer on a top surface of the riser, wherein the redistribution layer connects a lower portion of the one or more wire bonds with an upper portion of the one or more through riser vias, and wherein the threshold length is based on a target signal loss amount, a target inductance for the at least one of the one or more wire bonds, a target capacitance for the at least one of the one or more wire bonds, or a combination thereof.
6 . The system of claim 1 , wherein the riser comprises at least one of an integrated passive device or one or more passive surface mount devices.
7 . The system of claim 1 , wherein the riser comprises at least one of an active device or one or more passive surface mount devices.
8 . The system of claim 1 , wherein the one or more through riser vias are defined using lithography.
9 . The system of claim 1 , wherein the riser comprises a first redistribution layer on an upper or back surface of the riser and a second redistribution layer residing on a lower or front surface of the riser.
10 . The system of claim 9 , wherein the one or more through riser vias are coupled to both the first redistribution layer and the second redistribution layer.
11 . The system of claim 1 , wherein the riser is configured as a bumped or ball grid array construction and includes one or more pillars for surface mounting to the substrate.
12 . The system of claim 1 , wherein the riser has a height that matches a height of the plane of the device.
13 . The system of claim 1 , wherein a difference in height between the riser and the plane of the device is less than a predefined threshold.
14 . A riser, comprising: a body having first and second ends; one or more pillars or solder bumps on an underside of the body for facilitating mounting of the riser to a substrate; and one or more vias defined in the body and coupled to the one or more pillars or solder bumps, wherein mounting of the riser to the substrate enables connectivity of an interconnect of the substrate to be raised toward or to a plane of a device disposed over the substrate such that a wire bond for electrical coupling of the riser and the device has a length that is less than a threshold length, wherein the body is configured for being positioned partially over the interconnect which extends beyond the first end of the riser for coupling with one or more components, and wherein the body is configured for being positioned over the substrate and adjacent to the second end of the riser.
15 . The riser of claim 14 , wherein the riser includes a redistribution layer on a top surface of the riser, wherein the redistribution layer connects a lower portion of the one or more wire bonds with an upper portion of the one or more through riser vias, and wherein the threshold length is based on a target signal loss amount, a target inductance for the wire bond, a target capacitance for the wire bond, or a combination thereof.
16 . The riser of claim 14 , wherein the riser comprises at least one of an integrated passive device or one or more passive surface mount devices.
17 . The riser of claim 14 , wherein the riser comprises at least one of an active device or one or more passive surface mount devices.
18 . A method, comprising: mounting a riser over a first portion of a substrate, the riser being configured with one or more through riser vias for coupling to an interconnect of the substrate, the mounting causing the riser partially over the interconnect, such that the interconnect extends beyond a first end of the riser for coupling with one or more components; securing a device over a second portion of the substrate and adjacent to a second end of the riser, the device having one or more conductive contacts residing in a plane of the device; and providing one or more wire bonds that couple the one or more through riser vias with the one or more conductive contacts thereby enabling connectivity of the interconnect to be raised relative to the plane of the device such that at least one of the one or more wire bonds has a length that is less than a threshold length.
19 . The method of claim 18 , further comprising defining the one or more through riser vias in the riser using lithography, wherein the riser includes a redistribution layer on a top surface of the riser, wherein the redistribution layer connects a lower portion of the one or more wire bonds with an upper portion of the one or more through riser vias.
20 . The method of claim 18 , wherein the threshold length is based on a target signal loss amount, a target inductance for the at least one of the one or more wire bonds, a target capacitance for the at least one of the one or more wire bonds, or a combination thereof.

Description

FIELD OF THE DISCLOSURE The subject disclosure relates to an RF interconnect configuration for a substrate and a surface mount device. BACKGROUND Devices, such as electro-optic transmitters, such as Mach-Zehnder modulators, or opto-electric receivers, such as Intradyne Coherent Receiver (ICR) chips, are typically electrically coupled to a substrate via wire bonding. This provides an RF connection between the optical device and the substrate for data signal transfer. BRIEF DESCRIPTION OF THE DRAWINGS Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein: FIG. 1A is a block diagram illustrating an example, non-limiting embodiment of a system configuration in accordance with various aspects described herein. FIGS. 1B-1D are block diagrams illustrating other example, non-limiting embodiments of the system configuration in accordance with various aspects described herein. FIGS. 1E-1H are various views of an example, non-limiting embodiment of a system configuration in accordance with various aspects described herein. FIGS. 1I and 1J are perspective and cross-sectional views of a different system configured using wire bonding without a riser (or RF interconnect configuration), such as that as described herein. FIG. 1K illustrates different units of through riser vias in accordance with various aspects described herein. FIG. 1L is a graphical representation that illustrates various losses (across frequency) exhibited by a system configuration that employs a riser as compared to losses exhibited by a system configuration that employs traditional wire bonds without the use of such a riser. FIG. 1M illustrates example height mismatches between two components as well as corresponding resulting ball and stitch wire bonds formed using an arc capillary of particular dimensions in accordance with various aspects described herein. FIG. 1N illustrates an example of a ball and stitch wire bond where there is no height mismatch between two components in accordance with various aspects described herein. FIG. 1O illustrates example wedge bond loop profiles and lengths and an example wedge bond tool in accordance with various aspects described herein. FIG. 2 depicts an illustrative embodiment of a method in accordance with various aspects described herein. DETAILED DESCRIPTION In a high frequency application space (e.g., 65 gigahertz (GHz) or higher), wire bonds that are too physically long can lead to increased inductance, which can “choke” (or negatively impact) the high frequency data. Long wire bonds can also contribute to degraded channel to channel isolation, i.e. crosstalk between neighboring channels. Typically, transmitters and receivers are configured in quads or octals (i.e., Quad Parallel Mach-Zehnder (QPMZ)), where these arrays of transmitters and receivers are on a 450 micron (um), 500 um, or 625 um channel pitch. To achieve lower manufacturing costs of pluggable transceivers as well as improved throughput (i.e., increased parallelization or Baud rate), the hierarchy within devices is becoming more flattened. Turning a pluggable device into an optical configuration in this way can eliminate discrete optical-to-electrical (O-E)/electrical-to-optical (E-O) packages. This does not come without challenges, however, since, in the case of a transmitter thin-film lithium niobate (TFLN) modulator, the modulator must be directly interfaced to a transceiver printed circuit board (PCB) as opposed to being implemented in its own package with interfaces via pins or a flex. An existing technique involves simply mounting a transmitter TFLN modulator onto a top surface of a PCB. This unfortunately results in prohibitively long wire bonds for high frequency and high Baud operation. Another technique is to use controlled-depth mechanical or laser routing where several top layers of dielectric and metal are removed from the PCB while preserving the PCB backside real estate. The challenge with this technique is the difficulty in accurately routing the edges. Particularly, the edge of die becomes “pushed away” from the transmitter TFLN modulator and thus similarly results in prohibitively long wire bonds for high frequency and high Baud operation. For instance, in a case where the slope of the edge is about 15 degrees and the wire bond pad registration tolerance is about ±50 microns (um), the wire bond length can be larger as compared to other conventional interfaces by more than a hundred microns. As another option, the transmitter TFLN modulator may be positioned in a cut-out of a PCB transceiver board and wire bonded directly to the board. However, the repercussions of such an interfacing technique is that a large cut-out is required as well as fine precision mechanical routing in order for the bonding wires to be as short as possible for high frequency operation. Such routing through a cavity also reduces the available real estate on the backside of the transceiver PCB, which